From 1efe42fa97ed03662666cafee1b9dec9dfe524e9 Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Sat, 11 Oct 2014 16:18:51 -0500
Subject: stats: updates due to changes to x86, stale configs.

---
 .../arm/linux/realview-switcheroo-o3/config.ini    | 70 ++++++++++++++++++----
 1 file changed, 58 insertions(+), 12 deletions(-)

(limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini')

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
index 0248bee20..5d2c59c2a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
@@ -129,6 +129,7 @@ dstage2_mmu=system.cpu0.dstage2_mmu
 dtb=system.cpu0.dtb
 eventq_index=0
 fetchBufferSize=64
+fetchQueueSize=32
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -152,7 +153,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 needsTSO=false
 numIQEntries=64
-numPhysCCRegs=0
+numPhysCCRegs=1280
 numPhysFloatRegs=256
 numPhysIntRegs=256
 numROBEntries=192
@@ -182,7 +183,6 @@ switched_out=false
 system=system
 tracer=system.cpu0.tracer
 trapLatency=13
-wbDepth=1
 wbWidth=8
 workload=
 dcache_port=system.cpu0.dcache.cpu_side
@@ -733,6 +733,7 @@ dstage2_mmu=system.cpu1.dstage2_mmu
 dtb=system.cpu1.dtb
 eventq_index=0
 fetchBufferSize=64
+fetchQueueSize=32
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -756,7 +757,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 needsTSO=false
 numIQEntries=64
-numPhysCCRegs=0
+numPhysCCRegs=1280
 numPhysFloatRegs=256
 numPhysIntRegs=256
 numROBEntries=192
@@ -786,7 +787,6 @@ switched_out=true
 system=system
 tracer=system.cpu1.tracer
 trapLatency=13
-wbDepth=1
 wbWidth=8
 workload=
 
@@ -1247,13 +1247,13 @@ eventq_index=0
 sys=system
 
 [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
 header_cycles=1
 use_default_range=false
 width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
@@ -1278,7 +1278,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
 mem_side=system.membus.slave[2]
 
 [system.iocache.tags]
@@ -1327,11 +1327,12 @@ sequential_access=false
 size=4194304
 
 [system.membus]
-type=CoherentBus
+type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
 header_cycles=1
+snoop_filter=Null
 system=system
 use_default_range=false
 width=8
@@ -1359,8 +1360,33 @@ pio=system.membus.default
 
 [system.physmem]
 type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
 activation_limit=4
 addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
 channels=1
@@ -1369,6 +1395,7 @@ conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+dll=true
 eventq_index=0
 in_addr_map=true
 max_accesses_per_row=16
@@ -1382,19 +1409,26 @@ read_buffer_size=32
 static_backend_latency=10000
 static_frontend_latency=10000
 tBURST=5000
+tCCD_L=0
 tCK=1250
 tCL=13750
+tCS=2500
 tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=260000
 tRP=13750
 tRRD=6000
+tRRD_L=0
 tRTP=7500
 tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
 write_low_thresh_perc=50
@@ -1402,12 +1436,12 @@ port=system.membus.master[6]
 
 [system.realview]
 type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
 pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
 system=system
 
 [system.realview.a9scu]
@@ -1462,6 +1496,7 @@ HeaderType=0
 InterruptLine=31
 InterruptPin=1
 LatencyTimer=0
+LegacyIOBase=0
 MSICAPBaseOffset=0
 MSICAPCapId=0
 MSICAPMaskBits=0
@@ -1546,6 +1581,16 @@ pio_latency=100000
 system=system
 pio=system.iobus.master[9]
 
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
 [system.realview.flash_fake]
 type=IsaFake
 clk_domain=system.clk_domain
@@ -1864,10 +1909,11 @@ output=true
 port=3456
 
 [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 header_cycles=1
+snoop_filter=Null
 system=system
 use_default_range=false
 width=8
-- 
cgit v1.2.3