From 9954eb74df98c4749651eb78098595f78d642105 Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Sat, 4 Jul 2015 10:43:47 -0500
Subject: stats: update stale config.ini files, eio and few other stats.

---
 .../ref/arm/linux/realview64-o3-dual/config.ini    | 156 ++++++++++-----------
 1 file changed, 75 insertions(+), 81 deletions(-)

(limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual')

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
index 05f59cec5..d3e5a5093 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
@@ -212,7 +212,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -223,7 +223,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu0.dcache_port
 mem_side=system.cpu0.toL2Bus.slave[1]
@@ -295,9 +294,9 @@ opList=system.cpu0.fuPool.FUList0.opList
 [system.cpu0.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList1]
 type=FUDesc
@@ -309,23 +308,23 @@ opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 sys
 [system.cpu0.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu0.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList2]
 type=FUDesc
@@ -337,9 +336,9 @@ opList=system.cpu0.fuPool.FUList2.opList
 [system.cpu0.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList3]
 type=FUDesc
@@ -351,9 +350,9 @@ opList=system.cpu0.fuPool.FUList3.opList
 [system.cpu0.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList4]
 type=FUDesc
@@ -365,184 +364,184 @@ opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 s
 [system.cpu0.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu0.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu0.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu0.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu0.icache]
 type=BaseCache
@@ -554,7 +553,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -565,7 +564,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.cpu0.toL2Bus.slave[0]
@@ -665,7 +663,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -676,7 +674,6 @@ size=1048576
 system=system
 tags=system.cpu0.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.toL2Bus.master[0]
 mem_side=system.toL2Bus.slave[0]
@@ -849,7 +846,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -860,7 +857,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu1.dcache_port
 mem_side=system.cpu1.toL2Bus.slave[1]
@@ -932,9 +928,9 @@ opList=system.cpu1.fuPool.FUList0.opList
 [system.cpu1.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList1]
 type=FUDesc
@@ -946,23 +942,23 @@ opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 sys
 [system.cpu1.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu1.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList2]
 type=FUDesc
@@ -974,9 +970,9 @@ opList=system.cpu1.fuPool.FUList2.opList
 [system.cpu1.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList3]
 type=FUDesc
@@ -988,9 +984,9 @@ opList=system.cpu1.fuPool.FUList3.opList
 [system.cpu1.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList4]
 type=FUDesc
@@ -1002,184 +998,184 @@ opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 s
 [system.cpu1.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu1.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu1.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu1.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu1.icache]
 type=BaseCache
@@ -1191,7 +1187,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -1202,7 +1198,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.cpu1.toL2Bus.slave[0]
@@ -1302,7 +1297,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -1313,7 +1308,6 @@ size=1048576
 system=system
 tags=system.cpu1.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.toL2Bus.master[0]
 mem_side=system.toL2Bus.slave[1]
@@ -1416,7 +1410,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1427,7 +1421,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[3]
@@ -1452,7 +1445,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1463,7 +1456,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -1831,7 +1823,8 @@ pio=system.iobus.master[25]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -1861,6 +1854,7 @@ pio_latency=10000
 pixel_clock=7299
 system=system
 vnc=system.vncserver
+workaround_swap_rb=true
 dma=system.membus.slave[0]
 pio=system.iobus.master[5]
 
-- 
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