From 93c0307d418e08db609818f19f5d2b02d45e7465 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 29 Oct 2014 23:18:29 -0500 Subject: tests: Update regressions for the new kernels and various preceeding fixes. --- .../ref/x86/linux/pc-o3-timing/config.ini | 9 +++++---- .../fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr | 4 ++-- .../fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout | 12 ++++++------ .../10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 18 +++++++----------- .../ref/x86/linux/pc-switcheroo-full/config.ini | 9 +++++---- .../ref/x86/linux/pc-switcheroo-full/simerr | 5 +---- .../ref/x86/linux/pc-switcheroo-full/simout | 8 ++++---- .../ref/x86/linux/pc-switcheroo-full/stats.txt | 18 +++++++----------- 8 files changed, 37 insertions(+), 46 deletions(-) (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux') diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 68a408e3f..fe256a291 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1560,7 +1560,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1583,7 +1583,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1807,6 +1807,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr index 0067e63a5..0a8bc6fbe 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr @@ -1,11 +1,11 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 -warn: x86 cpuid: unimplemented function 8 -warn: x86 cpuid: unimplemented function 8 +warn: x86 cpuid: unknown family 0x8086 warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. warn: instruction 'wbinvd' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 86995b769..3b996a550 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:13:07 -gem5 started Jun 21 2014 22:16:40 -gem5 executing on phenom -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Oct 29 2014 09:18:07 +gem5 started Oct 29 2014 09:27:02 +gem5 executing on u200540-lin +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5.latest/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5137926173000 because m5_exit instruction encountered +Exiting @ tick 5125902116500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 5b52389f0..7d489dc5f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.125902 # Nu sim_ticks 5125902116500 # Number of ticks simulated final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 254798 # Simulator instruction rate (inst/s) -host_op_rate 503662 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3201100243 # Simulator tick rate (ticks/s) -host_mem_usage 749084 # Number of bytes of host memory used -host_seconds 1601.29 # Real time elapsed on the host +host_inst_rate 196886 # Simulator instruction rate (inst/s) +host_op_rate 389187 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2473535129 # Simulator tick rate (ticks/s) +host_mem_usage 743248 # Number of bytes of host memory used +host_seconds 2072.30 # Real time elapsed on the host sim_insts 408006726 # Number of instructions simulated sim_ops 806511598 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -426,8 +426,6 @@ system.iocache.fast_writes 46720 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses @@ -442,16 +440,14 @@ system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60928.460338 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60928.460338 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index 2c304759f..5c0ccd72f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5.latest/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1616,7 +1616,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1639,7 +1639,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1863,6 +1863,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index 56f83c534..b4d02041b 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -1,13 +1,10 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. -warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 -warn: x86 cpuid: unimplemented function 8 -warn: x86 cpuid: unimplemented function 8 warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. warn: instruction 'wbinvd' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout index 6a57a8844..ca2891ded 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:13:07 -gem5 started Jun 21 2014 22:18:32 -gem5 executing on phenom -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full +gem5 compiled Oct 29 2014 09:18:07 +gem5 started Oct 29 2014 09:28:19 +gem5 executing on u200540-lin +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5.latest/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index e53b3f285..847df0bf1 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.137752 # Nu sim_ticks 5137751757500 # Number of ticks simulated final_tick 5137751757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205879 # Simulator instruction rate (inst/s) -host_op_rate 409313 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4343855741 # Simulator tick rate (ticks/s) -host_mem_usage 976756 # Number of bytes of host memory used -host_seconds 1182.76 # Real time elapsed on the host +host_inst_rate 311526 # Simulator instruction rate (inst/s) +host_op_rate 619354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6572918502 # Simulator tick rate (ticks/s) +host_mem_usage 927072 # Number of bytes of host memory used +host_seconds 781.65 # Real time elapsed on the host sim_insts 243506025 # Number of instructions simulated sim_ops 484120527 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -854,8 +854,6 @@ system.iocache.fast_writes 46720 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 734 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 22056 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 22056 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::pc.south_bridge.ide 734 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 734 # number of overall MSHR misses @@ -870,16 +868,14 @@ system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93740027 system.iocache.overall_mshr_miss_latency::total 93740027 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.811947 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.472089 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.472089 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.811947 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.811947 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60294.715633 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60294.715633 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency -- cgit v1.2.3