From 868a8660426356a7d7e06e13391521290c8c20e4 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 4 Apr 2017 02:24:07 -0700 Subject: stats: Update the solaris boot stats for new snoopTraffic stat. The following change added the new stat: commit 0020662459fdd9efcfe9864ef12160515434ccdb Author: David Guillen Fandos Date: Thu Jul 21 17:19:14 2016 +0100 mem: Add snoop traffic statistic Change-Id: I9ee0fb4b8cc97c6b94e76ab5524f89c78c97d1a6 Reviewed-on: https://gem5-review.googlesource.com/2646 Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power --- .../sparc/solaris/t1000-simple-atomic/config.json | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json') diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json index 00d9dd136..d3a1b4f03 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json @@ -14,6 +14,7 @@ "p_state_clk_gate_bins": 20, "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", + "power_model": null, "latency_var": 0, "bandwidth": "0.000000", "conf_table_reported": true, @@ -46,6 +47,7 @@ "cxx_class": "Bridge", "req_size": 16, "clk_domain": "system.clk_domain", + "power_model": null, "delay": 100, "eventq_index": 0, "master": { @@ -71,6 +73,7 @@ "p_state_clk_gate_bins": 20, "cxx_class": "NoncoherentXBar", "clk_domain": "system.clk_domain", + "power_model": null, "width": 16, "eventq_index": 0, "master": { @@ -113,6 +116,7 @@ "cxx_class": "DumbTOD", "pio_latency": 200, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "eventq_index": 0, "time": "Thu Jan 1 00:00:00 2009", @@ -133,6 +137,7 @@ "cxx_class": "Uart8250", "pio_latency": 200, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "terminal": "system.t1000.pterm", "platform": "system.t1000", @@ -162,6 +167,7 @@ "p_state_clk_gate_max": 2000000000, "type": "IsaFake", "p_state_clk_gate_min": 2, + "power_model": null, "ret_data32": 4294967295, "path": "system.t1000.fake_membnks", "ret_data16": 65535, @@ -191,6 +197,7 @@ "p_state_clk_gate_max": 2000000000, "type": "IsaFake", "p_state_clk_gate_min": 2, + "power_model": null, "ret_data32": 4294967295, "path": "system.t1000.fake_jbi", "ret_data16": 65535, @@ -220,6 +227,7 @@ "p_state_clk_gate_max": 2000000000, "type": "IsaFake", "p_state_clk_gate_min": 2, + "power_model": null, "ret_data32": 4294967295, "path": "system.t1000.fake_l2esr_2", "ret_data16": 65535, @@ -262,6 +270,7 @@ "p_state_clk_gate_max": 2000000000, "type": "IsaFake", "p_state_clk_gate_min": 2, + "power_model": null, "ret_data32": 4294967295, "path": "system.t1000.fake_l2_4", "ret_data16": 65535, @@ -290,6 +299,7 @@ "p_state_clk_gate_max": 2000000000, "type": "IsaFake", "p_state_clk_gate_min": 2, + "power_model": null, "ret_data32": 4294967295, "path": "system.t1000.fake_l2_1", "ret_data16": 65535, @@ -318,6 +328,7 @@ "p_state_clk_gate_max": 2000000000, "type": "IsaFake", "p_state_clk_gate_min": 2, + "power_model": null, "ret_data32": 4294967295, "path": "system.t1000.fake_l2_2", "ret_data16": 65535, @@ -346,6 +357,7 @@ "p_state_clk_gate_max": 2000000000, "type": "IsaFake", "p_state_clk_gate_min": 2, + "power_model": null, "ret_data32": 4294967295, "path": "system.t1000.fake_l2_3", "ret_data16": 65535, @@ -378,6 +390,7 @@ "cxx_class": "Iob", "pio_latency": 2, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "platform": "system.t1000", "eventq_index": 0, @@ -397,6 +410,7 @@ "cxx_class": "Uart8250", "pio_latency": 200, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "terminal": "system.t1000.hterm", "platform": "system.t1000", @@ -427,6 +441,7 @@ "p_state_clk_gate_max": 2000000000, "type": "IsaFake", "p_state_clk_gate_min": 2, + "power_model": null, "ret_data32": 4294967295, "path": "system.t1000.fake_l2esr_3", "ret_data16": 65535, @@ -455,6 +470,7 @@ "p_state_clk_gate_max": 2000000000, "type": "IsaFake", "p_state_clk_gate_min": 2, + "power_model": null, "ret_data32": 4294967295, "path": "system.t1000.fake_ssi", "ret_data16": 65535, @@ -483,6 +499,7 @@ "p_state_clk_gate_max": 2000000000, "type": "IsaFake", "p_state_clk_gate_min": 2, + "power_model": null, "ret_data32": 4294967295, "path": "system.t1000.fake_l2esr_1", "ret_data16": 65535, @@ -511,6 +528,7 @@ "p_state_clk_gate_max": 2000000000, "type": "IsaFake", "p_state_clk_gate_min": 2, + "power_model": null, "ret_data32": 4294967295, "path": "system.t1000.fake_l2esr_4", "ret_data16": 65535, @@ -539,6 +557,7 @@ "p_state_clk_gate_max": 2000000000, "type": "IsaFake", "p_state_clk_gate_min": 2, + "power_model": null, "ret_data32": 4294967295, "path": "system.t1000.fake_clk", "ret_data16": 65535, @@ -585,6 +604,7 @@ "p_state_clk_gate_bins": 20, "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", + "power_model": null, "latency_var": 0, "bandwidth": "0.000000", "conf_table_reported": true, @@ -621,6 +641,7 @@ "p_state_clk_gate_bins": 20, "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", + "power_model": null, "latency_var": 0, "bandwidth": "0.000000", "conf_table_reported": true, @@ -659,6 +680,7 @@ "p_state_clk_gate_max": 2000000000, "type": "IsaFake", "p_state_clk_gate_min": 2, + "power_model": null, "ret_data32": 4294967295, "path": "system.membus.badaddr_responder", "ret_data16": 65535, @@ -700,6 +722,7 @@ }, "p_state_clk_gate_min": 2, "snoop_filter": null, + "power_model": null, "path": "system.membus", "snoop_response_latency": 4, "name": "membus", @@ -719,6 +742,7 @@ "p_state_clk_gate_bins": 20, "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", + "power_model": null, "latency_var": 0, "bandwidth": "0.000000", "conf_table_reported": true, @@ -776,6 +800,7 @@ "p_state_clk_gate_bins": 20, "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", + "power_model": null, "latency_var": 0, "bandwidth": "0.000000", "conf_table_reported": true, @@ -799,6 +824,7 @@ "p_state_clk_gate_bins": 20, "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", + "power_model": null, "latency_var": 0, "bandwidth": "0.000000", "conf_table_reported": true, @@ -814,6 +840,7 @@ "in_addr_map": true } ], + "power_model": null, "work_cpus_ckpt_count": 0, "thermal_components": [], "path": "system", @@ -887,6 +914,7 @@ "role": "MASTER" }, "socket_id": 0, + "power_model": null, "max_insts_all_threads": 0, "path": "system.cpu", "max_loads_any_thread": 0, @@ -961,6 +989,7 @@ "cxx_class": "MmDisk", "pio_latency": 200, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "eventq_index": 0, "default_p_state": "UNDEFINED", -- cgit v1.2.3