From e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Sun, 4 Jan 2015 13:02:12 -0600 Subject: stats: changes due to recent changesets. --- .../10.mcf/ref/arm/linux/minor-timing/config.ini | 7 + .../se/10.mcf/ref/arm/linux/minor-timing/stats.txt | 247 ++++++++++++--------- .../se/10.mcf/ref/arm/linux/o3-timing/config.ini | 31 ++- 3 files changed, 173 insertions(+), 112 deletions(-) (limited to 'tests/long/se/10.mcf/ref/arm/linux') diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini index 04ace1eeb..e8166ece0 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini @@ -132,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -591,6 +592,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -651,6 +653,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -700,6 +703,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -749,6 +753,7 @@ eventq_index=0 type=LiveProcess cmd=mcf mcf.in cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing +drivers= egid=100 env= errout=cerr @@ -757,6 +762,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -830,6 +836,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 52746e018..4f1cfb81e 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,26 +4,30 @@ sim_seconds 0.061494 # Nu sim_ticks 61493732000 # Number of ticks simulated final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271090 # Simulator instruction rate (inst/s) -host_op_rate 272440 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 183993432 # Simulator tick rate (ticks/s) -host_mem_usage 445016 # Number of bytes of host memory used -host_seconds 334.22 # Real time elapsed on the host +host_inst_rate 144123 # Simulator instruction rate (inst/s) +host_op_rate 144840 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 97818525 # Simulator tick rate (ticks/s) +host_mem_usage 433504 # Number of bytes of host memory used +host_seconds 628.65 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 996800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 49600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory system.physmem.bytes_read::total 996800 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 15575 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 16209782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 806586 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15403196 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 16209782 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 806586 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 806586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16209782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 806586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15403196 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 16209782 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15575 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted @@ -390,8 +394,8 @@ system.cpu.dcache.tags.total_refs 26267660 # To system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.644261 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20617906250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3616.604238 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.882960 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.604238 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.882960 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.882960 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id @@ -400,61 +404,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55463255 # Number of tag accesses system.cpu.dcache.tags.data_accesses 55463255 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 21598813 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 21598813 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21598813 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 4661073 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4661073 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4661073 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 26259886 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 26259886 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 26259886 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 26259886 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 26259886 # number of overall hits system.cpu.dcache.overall_hits::total 26259886 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 914958 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 914958 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 73908 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 73908 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 988866 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 988866 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 988866 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 988866 # number of overall misses system.cpu.dcache.overall_misses::total 988866 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910296994 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11910296994 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 11910296994 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345727500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2345727500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 2345727500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 14256024494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14256024494 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 14256024494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 14256024494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14256024494 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 14256024494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 22513771 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 22513771 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 27248752 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27248752 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 27248752 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 27248752 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27248752 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 27248752 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040640 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040640 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015609 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015609 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036290 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036290 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.315542 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13017.315542 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.478920 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31738.478920 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 14416.538231 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 14416.538231 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -466,45 +470,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks system.cpu.dcache.writebacks::total 943286 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11523 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11523 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 11523 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27140 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27140 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 38663 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38663 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 38663 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 38663 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38663 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 38663 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903435 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46768 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 950203 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 950203 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 950203 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958855506 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9958855506 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958855506 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333449750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1333449750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333449750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292305256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11292305256 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 11292305256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292305256 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11292305256 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 11292305256 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040128 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009877 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.322659 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11023.322659 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28512.011418 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28512.011418 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements @@ -599,9 +603,11 @@ system.cpu.l2cache.tags.sampled_refs 15558 # Sa system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885294 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.415381 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.469913 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027188 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020612 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006576 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id @@ -612,57 +618,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 903199 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 32224 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 935423 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 935423 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 935423 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 935397 # number of overall hits system.cpu.l2cache.overall_hits::total 935423 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15583 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15583 # 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number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46768 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46768 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 951006 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 803 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 950203 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 951006 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 803 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 950203 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001149 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967621 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.310982 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967621 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967621 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69012.752647 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67367.117117 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73893.129771 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65874.879675 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65874.879675 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -672,43 +696,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1031 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15575 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58331000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42469000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15862000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774515250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 774515250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774515250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832846250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42469000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 790377250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 832846250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832846250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42469000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 790377250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001140 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310982 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310982 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56577.109602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.709677 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61960.937500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53253.248762 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53253.248762 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 8fe365c4e..3203f61e7 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -157,6 +157,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -498,6 +499,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -558,6 +560,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -607,6 +610,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -628,19 +632,27 @@ mem_side=system.membus.slave[1] [system.cpu.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu.l2cache.tags] @@ -673,6 +685,7 @@ eventq_index=0 type=LiveProcess cmd=mcf mcf.in cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +drivers= egid=100 env= errout=cerr @@ -681,6 +694,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -754,6 +768,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 -- cgit v1.2.3