From 53a05978054ac9bb718e419a48371bd10c720267 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Mon, 11 Mar 2013 17:45:09 -0500 Subject: regressions: x86: stats updates due to new x87 insts --- .../ref/x86/linux/simple-timing/stats.txt | 76 +++++++++++----------- 1 file changed, 38 insertions(+), 38 deletions(-) (limited to 'tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt') diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 532eed382..c3c3c6909 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.647873 # Number of seconds simulated -sim_ticks 1647872848000 # Number of ticks simulated -final_tick 1647872848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1647872849000 # Number of ticks simulated +final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 579757 # Simulator instruction rate (inst/s) -host_op_rate 1072035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1155389699 # Simulator tick rate (ticks/s) -host_mem_usage 301076 # Number of bytes of host memory used -host_seconds 1426.25 # Real time elapsed on the host +host_inst_rate 379189 # Simulator instruction rate (inst/s) +host_op_rate 701163 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 755680972 # Simulator tick rate (ticks/s) +host_mem_usage 300836 # Number of bytes of host memory used +host_seconds 2180.65 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated -sim_ops 1528988701 # Number of ops (including micro ops) simulated +sim_ops 1528988702 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory @@ -35,26 +35,26 @@ system.physmem.bw_total::cpu.inst 73248 # To system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3295745696 # number of cpu cycles simulated +system.cpu.numCycles 3295745698 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed -system.cpu.committedOps 1528988701 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317560 # Number of integer alu accesses +system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317560 # number of integer instructions +system.cpu.num_int_insts 1528317562 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3855106255 # number of times the integer registers were read -system.cpu.num_int_register_writes 1614040852 # number of times the integer registers were written +system.cpu.num_int_register_reads 3855106260 # number of times the integer registers were read +system.cpu.num_int_register_writes 1614040854 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 533262342 # number of memory refs -system.cpu.num_load_insts 384102156 # Number of load instructions +system.cpu.num_mem_refs 533262343 # number of memory refs +system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3295745696 # Number of busy cycles +system.cpu.num_busy_cycles 3295745698 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1253 # number of replacements @@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 348459 # number of replacements -system.cpu.l2cache.tagsinuse 29286.402681 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29286.402664 # Cycle average of tags in use system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 755936430000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21041.299350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 139.758520 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8105.344812 # Average occupied blocks per requestor +system.cpu.l2cache.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy @@ -274,22 +274,22 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.415786 # Cycle average of tags in use -system.cpu.dcache.total_refs 530743929 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4086.415783 # Cycle average of tags in use +system.cpu.dcache.total_refs 530743930 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8211723000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.415786 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530743929 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530743929 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530743929 # number of overall hits -system.cpu.dcache.overall_hits::total 530743929 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits +system.cpu.dcache.overall_hits::total 530743930 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses @@ -306,14 +306,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533262387 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533262387 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533262387 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533262387 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses -- cgit v1.2.3