From 0d46708dc20c438d29bd724fb7d4b54d4d2f318a Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 13 Feb 2012 12:30:30 -0600 Subject: bp: fix up stats for changes to branch predictor --- .../se/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 1048 ++++++++++---------- 1 file changed, 524 insertions(+), 524 deletions(-) (limited to 'tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt') diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index e5ff3033e..54f4ab1b0 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.089480 # Number of seconds simulated -sim_ticks 89480174500 # Number of ticks simulated -final_tick 89480174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.080257 # Number of seconds simulated +sim_ticks 80257421500 # Number of ticks simulated +final_tick 80257421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246728 # Simulator instruction rate (inst/s) -host_op_rate 246728 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58782597 # Simulator tick rate (ticks/s) -host_mem_usage 216860 # Number of bytes of host memory used -host_seconds 1522.22 # Real time elapsed on the host -sim_insts 375574794 # Number of instructions simulated -sim_ops 375574794 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 475840 # Number of bytes read from this memory -system.physmem.bytes_inst_read 219968 # Number of instructions bytes read from this memory +host_inst_rate 261701 # Simulator instruction rate (inst/s) +host_op_rate 261701 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55923550 # Simulator tick rate (ticks/s) +host_mem_usage 217092 # Number of bytes of host memory used +host_seconds 1435.13 # Real time elapsed on the host +sim_insts 375574808 # Number of instructions simulated +sim_ops 375574808 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 478528 # Number of bytes read from this memory +system.physmem.bytes_inst_read 222720 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7435 # Number of read requests responded to by this memory +system.physmem.num_reads 7477 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 5317826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2458288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 5317826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 5962414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 2775070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 5962414 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 105444914 # DTB read hits -system.cpu.dtb.read_misses 94699 # DTB read misses -system.cpu.dtb.read_acv 48617 # DTB read access violations -system.cpu.dtb.read_accesses 105539613 # DTB read accesses -system.cpu.dtb.write_hits 79763652 # DTB write hits -system.cpu.dtb.write_misses 1536 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 79765188 # DTB write accesses -system.cpu.dtb.data_hits 185208566 # DTB hits -system.cpu.dtb.data_misses 96235 # DTB misses -system.cpu.dtb.data_acv 48618 # DTB access violations -system.cpu.dtb.data_accesses 185304801 # DTB accesses -system.cpu.itb.fetch_hits 57904086 # ITB hits -system.cpu.itb.fetch_misses 346 # ITB misses +system.cpu.dtb.read_hits 103368572 # DTB read hits +system.cpu.dtb.read_misses 88956 # DTB read misses +system.cpu.dtb.read_acv 48603 # DTB read access violations +system.cpu.dtb.read_accesses 103457528 # DTB read accesses +system.cpu.dtb.write_hits 78975243 # DTB write hits +system.cpu.dtb.write_misses 1664 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 78976907 # DTB write accesses +system.cpu.dtb.data_hits 182343815 # DTB hits +system.cpu.dtb.data_misses 90620 # DTB misses +system.cpu.dtb.data_acv 48606 # DTB access violations +system.cpu.dtb.data_accesses 182434435 # DTB accesses +system.cpu.itb.fetch_hits 52487109 # ITB hits +system.cpu.itb.fetch_misses 461 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 57904432 # ITB accesses +system.cpu.itb.fetch_accesses 52487570 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,315 +53,315 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 178960351 # number of cpu cycles simulated +system.cpu.numCycles 160514845 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 56765606 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 33143039 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3552012 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 40427205 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 32022628 # Number of BTB hits +system.cpu.BPredUnit.lookups 52017212 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 30261257 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1593315 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 28494887 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24272738 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 10686505 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1330 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 59866357 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 502938652 # Number of instructions fetch has processed -system.cpu.fetch.Branches 56765606 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42709133 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 93526616 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12701088 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 16326839 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7643 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 57904086 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1110763 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 178838548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.812250 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.245901 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9355488 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 4145 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 53524792 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 462212886 # Number of instructions fetch has processed +system.cpu.fetch.Branches 52017212 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33628226 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81457148 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7754706 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19283001 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7777 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 52487109 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 628108 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 160395311 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.881711 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314748 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 85311932 47.70% 47.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8035871 4.49% 52.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9868460 5.52% 57.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6372149 3.56% 61.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13508487 7.55% 68.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9517347 5.32% 74.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5905302 3.30% 77.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3555081 1.99% 79.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36763919 20.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78938163 49.21% 49.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4375676 2.73% 51.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7263628 4.53% 56.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5613511 3.50% 59.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12408314 7.74% 67.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8080182 5.04% 72.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5692573 3.55% 76.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1906295 1.19% 77.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36116969 22.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 178838548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317197 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.810336 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 65738845 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12641259 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 87702735 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3649079 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9106630 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 10252982 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4580 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 491283130 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12139 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9106630 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 70077435 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4396073 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 392991 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 87026850 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7838569 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 478183111 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 34338 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 6474620 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 310467420 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 626927534 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 331115388 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 295812146 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 50935101 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38371 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 296 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21811876 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 110641644 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 85552281 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8662202 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5906832 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 433013718 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 418626838 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2003473 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 56038444 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 32198216 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 178838548 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.340809 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.008173 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 160395311 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324065 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.879565 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 59060129 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 14738019 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76660368 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3818816 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6117979 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9735972 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4512 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 456714619 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12671 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6117979 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62341788 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4786215 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 392111 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 77312738 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9444480 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 451064099 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26210 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7820126 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 294805500 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 593185508 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 313931497 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 279254011 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35273171 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38670 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 424 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27284397 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106956708 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81779793 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8927292 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6395845 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 416292628 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 359 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407676624 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1078526 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 40464590 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 19834312 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 144 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 160395311 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.541699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.006909 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 44336411 24.79% 24.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 29007268 16.22% 41.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 27775406 15.53% 56.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 26238037 14.67% 71.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22251353 12.44% 83.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15664112 8.76% 92.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8263195 4.62% 97.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3972623 2.22% 99.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1330143 0.74% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 31984575 19.94% 19.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26488225 16.51% 36.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26058764 16.25% 52.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24758572 15.44% 68.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21531957 13.42% 81.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15472386 9.65% 91.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8703569 5.43% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4094121 2.55% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1303142 0.81% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 178838548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 160395311 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 135690 1.14% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 41926 0.35% 1.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 2442 0.02% 1.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 8992 0.08% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1877041 15.76% 17.34% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1762283 14.79% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5120089 42.98% 75.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2964035 24.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35479 0.30% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 74583 0.63% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5020 0.04% 0.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3238 0.03% 1.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1852472 15.62% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1780365 15.01% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5090382 42.92% 74.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3018331 25.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 164031789 39.18% 39.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126165 0.51% 39.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33716465 8.05% 47.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7893369 1.89% 49.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2899949 0.69% 50.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16711518 3.99% 54.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1573138 0.38% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 108174365 25.84% 80.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 81466499 19.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 157965890 38.75% 38.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126519 0.52% 39.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33457651 8.21% 47.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7841942 1.92% 49.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2840834 0.70% 50.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16563363 4.06% 54.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1591033 0.39% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105252822 25.82% 80.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80002989 19.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 418626838 # Type of FU issued -system.cpu.iq.rate 2.339216 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11912498 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028456 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 681277012 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 289109429 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 241633599 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 348731183 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 199993522 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 164553982 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 252486483 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 178019272 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13980098 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407676624 # Type of FU issued +system.cpu.iq.rate 2.539806 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11859870 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029091 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 647408174 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 269506276 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237627844 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 341278781 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187302066 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162920489 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 245219921 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 174282992 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14797631 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 15887158 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 143607 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 50570 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12031553 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12202221 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 124163 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 50788 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8259064 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 233419 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260903 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9106630 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2382208 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 372749 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 458676643 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2278358 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 110641644 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 85552281 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 129 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 50570 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3441219 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 544657 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3985876 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 409944817 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 105588265 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 8682021 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6117979 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2500869 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 370633 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 441236152 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 174981 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106956708 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81779793 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 359 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 125 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 50788 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1245732 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 559417 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1805149 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403162552 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103506235 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4514072 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 25662667 # number of nop insts executed -system.cpu.iew.exec_refs 185353481 # number of memory reference insts executed -system.cpu.iew.exec_branches 48120403 # Number of branches executed -system.cpu.iew.exec_stores 79765216 # Number of stores executed -system.cpu.iew.exec_rate 2.290702 # Inst execution rate -system.cpu.iew.wb_sent 407421919 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 406187581 # cumulative count of insts written-back -system.cpu.iew.wb_producers 197894075 # num instructions producing a value -system.cpu.iew.wb_consumers 277422150 # num instructions consuming a value +system.cpu.iew.exec_nop 24943165 # number of nop insts executed +system.cpu.iew.exec_refs 182483180 # number of memory reference insts executed +system.cpu.iew.exec_branches 47188511 # Number of branches executed +system.cpu.iew.exec_stores 78976945 # Number of stores executed +system.cpu.iew.exec_rate 2.511684 # Inst execution rate +system.cpu.iew.wb_sent 401387937 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400548333 # cumulative count of insts written-back +system.cpu.iew.wb_producers 195210305 # num instructions producing a value +system.cpu.iew.wb_consumers 273275997 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.269707 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713332 # average fanout of values written-back +system.cpu.iew.wb_rate 2.495397 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.714334 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions -system.cpu.commit.commitCommittedOps 398664569 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 60016815 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 398664583 # The number of committed instructions +system.cpu.commit.commitCommittedOps 398664583 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 42606114 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3547729 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 169731918 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.348790 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.858024 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1588886 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 154277332 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.584078 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.967872 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 70140218 41.32% 41.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 25651558 15.11% 56.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14667534 8.64% 65.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12267165 7.23% 72.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 9098146 5.36% 77.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6161287 3.63% 81.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5543706 3.27% 84.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3203239 1.89% 86.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22999065 13.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58795294 38.11% 38.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 23338616 15.13% 53.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13263185 8.60% 61.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11678899 7.57% 69.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8438473 5.47% 74.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5481478 3.55% 78.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5137622 3.33% 81.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3374234 2.19% 83.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24769531 16.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 169731918 # Number of insts commited each cycle -system.cpu.commit.committedInsts 398664569 # Number of instructions committed -system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 154277332 # Number of insts commited each cycle +system.cpu.commit.committedInsts 398664583 # Number of instructions committed +system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 168275214 # Number of memory references committed -system.cpu.commit.loads 94754486 # Number of loads committed +system.cpu.commit.refs 168275216 # Number of memory references committed +system.cpu.commit.loads 94754487 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 44587530 # Number of branches committed +system.cpu.commit.branches 44587533 # Number of branches committed system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. -system.cpu.commit.int_insts 316365825 # Number of committed integer instructions. +system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22999065 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 24769531 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 605411260 # The number of ROB reads -system.cpu.rob.rob_writes 926487800 # The number of ROB writes -system.cpu.timesIdled 2712 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 121803 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 375574794 # Number of Instructions Simulated -system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated -system.cpu.cpi 0.476497 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.476497 # CPI: Total CPI of All Threads -system.cpu.ipc 2.098648 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.098648 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 409675274 # number of integer regfile reads -system.cpu.int_regfile_writes 175727060 # number of integer regfile writes -system.cpu.fp_regfile_reads 159328411 # number of floating regfile reads -system.cpu.fp_regfile_writes 105866122 # number of floating regfile writes +system.cpu.rob.rob_reads 570775521 # The number of ROB reads +system.cpu.rob.rob_writes 888672842 # The number of ROB writes +system.cpu.timesIdled 2679 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 119534 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 375574808 # Number of Instructions Simulated +system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated +system.cpu.cpi 0.427384 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.427384 # CPI: Total CPI of All Threads +system.cpu.ipc 2.339814 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.339814 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 402674037 # number of integer regfile reads +system.cpu.int_regfile_writes 172514061 # number of integer regfile writes +system.cpu.fp_regfile_reads 158318736 # number of floating regfile reads +system.cpu.fp_regfile_writes 105208261 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2110 # number of replacements -system.cpu.icache.tagsinuse 1834.326922 # Cycle average of tags in use -system.cpu.icache.total_refs 57898804 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4037 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14342.037156 # Average number of references to valid blocks. +system.cpu.icache.replacements 2234 # number of replacements +system.cpu.icache.tagsinuse 1837.389415 # Cycle average of tags in use +system.cpu.icache.total_refs 52481453 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4164 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12603.615034 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1834.326922 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.895667 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.895667 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 57898804 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 57898804 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 57898804 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 57898804 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 57898804 # number of overall hits -system.cpu.icache.overall_hits::total 57898804 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5282 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5282 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5282 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5282 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5282 # number of overall misses -system.cpu.icache.overall_misses::total 5282 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 167914000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 167914000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 167914000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 167914000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 167914000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 167914000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57904086 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57904086 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57904086 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57904086 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57904086 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57904086 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000091 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000091 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000091 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31789.852329 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1837.389415 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.897163 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.897163 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 52481453 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 52481453 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 52481453 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 52481453 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 52481453 # number of overall hits +system.cpu.icache.overall_hits::total 52481453 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5656 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5656 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5656 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5656 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5656 # number of overall misses +system.cpu.icache.overall_misses::total 5656 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 175405000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 175405000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 175405000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 175405000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 175405000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 175405000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 52487109 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 52487109 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 52487109 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 52487109 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 52487109 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 52487109 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000108 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000108 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000108 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31012.199434 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,202 +370,202 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1245 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1245 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1245 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1245 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1245 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1245 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4037 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4037 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4037 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4037 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4037 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4037 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123459000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 123459000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123459000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 123459000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123459000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 123459000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30581.867724 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30581.867724 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30581.867724 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1492 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1492 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1492 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1492 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1492 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1492 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4164 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4164 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4164 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4164 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4164 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4164 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125153000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 125153000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125153000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 125153000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125153000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 125153000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30055.955812 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30055.955812 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30055.955812 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 793 # number of replacements -system.cpu.dcache.tagsinuse 3296.196945 # Cycle average of tags in use -system.cpu.dcache.total_refs 164730953 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4193 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 39287.134033 # Average number of references to valid blocks. +system.cpu.dcache.replacements 804 # number of replacements +system.cpu.dcache.tagsinuse 3297.800145 # Cycle average of tags in use +system.cpu.dcache.total_refs 161809566 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4205 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38480.277289 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3296.196945 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804736 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804736 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 91229707 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 91229707 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501239 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501239 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 164730946 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 164730946 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 164730946 # number of overall hits -system.cpu.dcache.overall_hits::total 164730946 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1678 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1678 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19489 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19489 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21167 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21167 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21167 # number of overall misses -system.cpu.dcache.overall_misses::total 21167 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55919500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55919500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 568883000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 568883000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 624802500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 624802500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 624802500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 624802500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 91231385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 91231385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 164752113 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 164752113 # 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number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 161809550 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161809550 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161809550 # number of overall hits +system.cpu.dcache.overall_hits::total 161809550 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1689 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1689 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19511 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19511 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21200 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21200 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21200 # number of overall misses +system.cpu.dcache.overall_misses::total 21200 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56020500 # 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number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 161830750 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161830750 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161830750 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161830750 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33325.089392 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 234231000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108421000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125810000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 234231000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867398 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.976577 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.835735 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.950535 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31155.459770 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31425.287356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31490.246242 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31155.459770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31476.107080 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- -- cgit v1.2.3