From a217eba078b17c51f6a74c9237584f066ef78bf1 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Wed, 3 Sep 2014 07:42:59 -0400 Subject: stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches. --- .../30.eon/ref/arm/linux/simple-timing/stats.txt | 492 +++++++++++---------- 1 file changed, 258 insertions(+), 234 deletions(-) (limited to 'tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt') diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 23ba68f1d..57cca8ea4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.525834 # Number of seconds simulated -sim_ticks 525834342000 # Number of ticks simulated -final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517235 # Number of seconds simulated +sim_ticks 517235411000 # Number of ticks simulated +final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 605985 # Simulator instruction rate (inst/s) -host_op_rate 774729 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1168322503 # Simulator tick rate (ticks/s) -host_mem_usage 318808 # Number of bytes of host memory used -host_seconds 450.08 # Real time elapsed on the host -sim_insts 272739283 # Number of instructions simulated -sim_ops 348687122 # Number of ops (including micro ops) simulated +host_inst_rate 749544 # Simulator instruction rate (inst/s) +host_op_rate 899855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1421469107 # Simulator tick rate (ticks/s) +host_mem_usage 324416 # Number of bytes of host memory used +host_seconds 363.87 # Real time elapsed on the host +sim_insts 272739285 # Number of instructions simulated +sim_ops 327433743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory @@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total 166976 # Nu system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 831532 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 845356 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3976 # Transaction distribution system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution @@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 437248 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -130,73 +130,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1051668684 # number of cpu cycles simulated +system.cpu.numCycles 1034470822 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 272739283 # Number of instructions committed -system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses +system.cpu.committedInsts 272739285 # Number of instructions committed +system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12448615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls -system.cpu.num_int_insts 279584917 # number of integer instructions +system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls +system.cpu.num_int_insts 258331537 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read -system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written +system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read +system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_mem_refs 177024356 # number of memory refs -system.cpu.num_load_insts 94648757 # Number of load instructions +system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read +system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written +system.cpu.num_mem_refs 168107847 # number of memory refs +system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1051668684 # Number of busy cycles +system.cpu.num_busy_cycles 1034470822 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 30563501 # Number of branches fetched +system.cpu.Branches 30563502 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 116649413 33.42% 33.42% # Class of executed instruction -system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction -system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction -system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction +system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction +system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 349065592 # Class of executed instruction +system.cpu.op_class::total 327812213 # Class of executed instruction system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id @@ -204,44 +206,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 26 system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 697336303 # Number of tag accesses -system.cpu.icache.tags.data_accesses 697336303 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits -system.cpu.icache.overall_hits::total 348644747 # number of overall hits +system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses +system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits +system.cpu.icache.overall_hits::total 348644749 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -256,38 +258,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id @@ -321,17 +323,17 @@ system.cpu.l2cache.demand_misses::total 6832 # nu system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135668000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) @@ -356,17 +358,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -386,17 +388,17 @@ system.cpu.l2cache.demand_mshr_misses::total 6832 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses @@ -408,92 +410,100 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 353296632 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 353296632 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits -system.cpu.dcache.overall_hits::total 176619809 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits +system.cpu.dcache.overall_hits::total 168337827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses -system.cpu.dcache.overall_misses::total 4478 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses +system.cpu.dcache.overall_misses::total 4479 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -504,40 +514,54 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 998 # number of writebacks system.cpu.dcache.writebacks::total 998 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 2608205 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution -- cgit v1.2.3