From 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 15 Oct 2012 08:09:54 -0400 Subject: Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches. --- .../40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1208 ++++++++++---------- 1 file changed, 604 insertions(+), 604 deletions(-) (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt') diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index b1563a03b..70391a345 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.653191 # Number of seconds simulated -sim_ticks 653190727500 # Number of ticks simulated -final_tick 653190727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.659244 # Number of seconds simulated +sim_ticks 659244465000 # Number of ticks simulated +final_tick 659244465000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90710 # Simulator instruction rate (inst/s) -host_op_rate 123535 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42799734 # Simulator tick rate (ticks/s) -host_mem_usage 235092 # Number of bytes of host memory used -host_seconds 15261.56 # Real time elapsed on the host -sim_insts 1384379220 # Number of instructions simulated -sim_ops 1885333972 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 203328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94517952 # Number of bytes read from this memory -system.physmem.bytes_read::total 94721280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 203328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 203328 # Number of instructions bytes read from this memory +host_inst_rate 88407 # Simulator instruction rate (inst/s) +host_op_rate 120399 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42099861 # Simulator tick rate (ticks/s) +host_mem_usage 243836 # Number of bytes of host memory used +host_seconds 15659.07 # Real time elapsed on the host +sim_insts 1384375635 # Number of instructions simulated +sim_ops 1885330387 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 199616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94515200 # Number of bytes read from this memory +system.physmem.bytes_read::total 94714816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 199616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 199616 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3177 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476843 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1480020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3119 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476800 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1479919 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 311284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 144701919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 145013204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 311284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 311284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6476418 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6476418 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6476418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 311284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 144701919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 151489621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 302795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 143368970 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 143671765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302795 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302795 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6416946 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6416946 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6416946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 143368970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 150088711 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,320 +77,320 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1306381456 # number of cpu cycles simulated +system.cpu.numCycles 1318488931 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 451886525 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 356592173 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 33205003 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 281633187 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 237475635 # Number of BTB hits +system.cpu.BPredUnit.lookups 461326092 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 364071075 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 34100101 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 298580925 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 245422956 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 53725762 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2808142 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 371691213 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2329385713 # Number of instructions fetch has processed -system.cpu.fetch.Branches 451886525 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 291201397 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 621090552 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 170450530 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 138693587 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 29461 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 349470928 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11301689 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1268700671 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.542231 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.167897 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 54976315 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2806988 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 381926912 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2354617227 # Number of instructions fetch has processed +system.cpu.fetch.Branches 461326092 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 300399271 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 631966560 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 174781634 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 133381872 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1547 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 26290 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 359560180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11891763 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1287933807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.529860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.156146 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 647656502 51.05% 51.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 44886599 3.54% 54.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 100617653 7.93% 62.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 60404416 4.76% 67.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 73875113 5.82% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 44960792 3.54% 76.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31035484 2.45% 79.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30635125 2.41% 81.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 234628987 18.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 656012764 50.94% 50.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47127862 3.66% 54.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 105351348 8.18% 62.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 60429666 4.69% 67.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 75027065 5.83% 73.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45419751 3.53% 76.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32157937 2.50% 79.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 32241388 2.50% 81.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 234166026 18.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1268700671 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.345907 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.783082 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 423570129 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 110130146 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 579255946 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18563929 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 137180521 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 50568077 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 14826 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3119517279 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28937 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 137180521 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 460603750 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40419610 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 499687 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 558753819 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71243284 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3033648086 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 193 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4887381 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56133943 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1685 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2996122982 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14446186472 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13843342856 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 602843616 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993153898 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1002969084 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 28984 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24876 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 185421286 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 977548256 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 509159433 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36902722 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 39166460 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2862588309 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35911 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2484024411 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13118317 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 964784903 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2432051802 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12801 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1268700671 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.957928 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.885204 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1287933807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.349890 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.785845 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433461682 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105761116 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 591844441 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16248270 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 140618298 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 52072887 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12605 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3150187282 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 23939 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 140618298 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 469309271 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39277977 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 483250 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 570159229 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 68085782 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3069262221 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 155 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4380621 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 54394099 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1922 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3038163295 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14611934802 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13977694721 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 634240081 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993148162 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1045015133 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27322 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23140 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 179514029 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 982659180 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 514844433 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 35819898 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36120464 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2890303698 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 33130 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2506565055 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17234382 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 992532581 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2476785189 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 10737 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1287933807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.946191 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.883330 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 413577866 32.60% 32.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 194484687 15.33% 47.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 205713957 16.21% 64.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 171271635 13.50% 77.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 131142170 10.34% 87.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 97400688 7.68% 95.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37845090 2.98% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12462379 0.98% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4802199 0.38% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 425460645 33.03% 33.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 193710960 15.04% 48.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 207680071 16.13% 64.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 174651445 13.56% 77.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 137124890 10.65% 88.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 94993427 7.38% 95.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 35869114 2.79% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12687801 0.99% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5755454 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1268700671 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1287933807 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 960888 1.05% 1.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23894 0.03% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55821815 60.83% 61.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 34963808 38.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 692420 0.75% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24115 0.03% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 56113360 61.04% 61.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 35101326 38.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1133289530 45.62% 45.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11232040 0.45% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876506 0.28% 46.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5503108 0.22% 46.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23588545 0.95% 47.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 841636528 33.88% 81.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 460522863 18.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1147061112 45.76% 45.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11228333 0.45% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876483 0.27% 46.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5512765 0.22% 46.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 16 0.00% 46.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23755231 0.95% 47.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 846734490 33.78% 81.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 464021335 18.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2484024411 # Type of FU issued -system.cpu.iq.rate 1.901454 # Inst issue rate -system.cpu.iq.fu_busy_cnt 91770405 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036944 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6213658406 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3738455000 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2292430207 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 127979809 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 89021624 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 58699426 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2509271154 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 66523662 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 80303664 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2506565055 # Type of FU issued +system.cpu.iq.rate 1.901089 # Inst issue rate +system.cpu.iq.fu_busy_cnt 91931221 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036676 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6281789129 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3788847878 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2312502456 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 128440391 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 94088071 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 58648289 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2531838073 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 66658203 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 81288215 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 346159349 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5258 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1403998 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 232162410 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 351270990 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24451 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1405210 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 237848127 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 137180521 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17480517 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1686547 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2862638347 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 10688123 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 977548256 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 509159433 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24752 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1673918 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2091 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1403998 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 34817527 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1757167 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 36574694 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2405136648 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 795998932 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 78887763 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 140618298 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16819525 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1547443 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2890351322 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8718298 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 982659180 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 514844433 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22537 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1538114 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1067 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1405210 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 36121914 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2298987 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 38420901 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2424696979 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 800223206 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 81868076 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14127 # number of nop insts executed -system.cpu.iew.exec_refs 1234173393 # number of memory reference insts executed -system.cpu.iew.exec_branches 329367580 # Number of branches executed -system.cpu.iew.exec_stores 438174461 # Number of stores executed -system.cpu.iew.exec_rate 1.841068 # Inst execution rate -system.cpu.iew.wb_sent 2376887575 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2351129633 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1360698402 # num instructions producing a value -system.cpu.iew.wb_consumers 2562363668 # num instructions consuming a value +system.cpu.iew.exec_nop 14494 # number of nop insts executed +system.cpu.iew.exec_refs 1240121255 # number of memory reference insts executed +system.cpu.iew.exec_branches 334180264 # Number of branches executed +system.cpu.iew.exec_stores 439898049 # Number of stores executed +system.cpu.iew.exec_rate 1.838997 # Inst execution rate +system.cpu.iew.wb_sent 2396725321 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2371150745 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1368219909 # num instructions producing a value +system.cpu.iew.wb_consumers 2564381587 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.799727 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.531033 # average fanout of values written-back +system.cpu.iew.wb_rate 1.798385 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533548 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 977293768 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 23110 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 33191422 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1131520152 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.666205 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.368466 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 1005010225 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 22393 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 34087773 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1147315511 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.643263 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.351044 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 484597847 42.83% 42.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 298921465 26.42% 69.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90821305 8.03% 77.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 72269012 6.39% 83.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 45034307 3.98% 87.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23256378 2.06% 89.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15793077 1.40% 91.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9817791 0.87% 91.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 91008970 8.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 497187613 43.33% 43.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 300050723 26.15% 69.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 93458742 8.15% 77.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 72384885 6.31% 83.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 45393865 3.96% 87.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22818775 1.99% 89.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15801520 1.38% 91.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11015018 0.96% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89204370 7.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1131520152 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384390236 # Number of instructions committed -system.cpu.commit.committedOps 1885344988 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1147315511 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384386651 # Number of instructions committed +system.cpu.commit.committedOps 1885341403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385930 # Number of memory references committed -system.cpu.commit.loads 631388907 # Number of loads committed +system.cpu.commit.refs 908384496 # Number of memory references committed +system.cpu.commit.loads 631388190 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 299636121 # Number of branches committed +system.cpu.commit.branches 299635404 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705771 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653702903 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 91008970 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 89204370 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3903131593 # The number of ROB reads -system.cpu.rob.rob_writes 5862472148 # The number of ROB writes -system.cpu.timesIdled 1341228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 37680785 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384379220 # Number of Instructions Simulated -system.cpu.committedOps 1885333972 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384379220 # Number of Instructions Simulated -system.cpu.cpi 0.943659 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.943659 # CPI: Total CPI of All Threads -system.cpu.ipc 1.059705 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.059705 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11952036932 # number of integer regfile reads -system.cpu.int_regfile_writes 2256711080 # number of integer regfile writes -system.cpu.fp_regfile_reads 70681119 # number of floating regfile reads -system.cpu.fp_regfile_writes 50325350 # number of floating regfile writes -system.cpu.misc_regfile_reads 3723531681 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776354 # number of misc regfile writes -system.cpu.icache.replacements 23459 # number of replacements -system.cpu.icache.tagsinuse 1656.238339 # Cycle average of tags in use -system.cpu.icache.total_refs 349436364 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 25154 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13891.880576 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3948444424 # The number of ROB reads +system.cpu.rob.rob_writes 5921335810 # The number of ROB writes +system.cpu.timesIdled 1335770 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30555124 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384375635 # Number of Instructions Simulated +system.cpu.committedOps 1885330387 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384375635 # Number of Instructions Simulated +system.cpu.cpi 0.952407 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.952407 # CPI: Total CPI of All Threads +system.cpu.ipc 1.049971 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.049971 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12040516185 # number of integer regfile reads +system.cpu.int_regfile_writes 2278755627 # number of integer regfile writes +system.cpu.fp_regfile_reads 70304928 # number of floating regfile reads +system.cpu.fp_regfile_writes 50983418 # number of floating regfile writes +system.cpu.misc_regfile_reads 3755360027 # number of misc regfile reads +system.cpu.misc_regfile_writes 13774920 # number of misc regfile writes +system.cpu.icache.replacements 22971 # number of replacements +system.cpu.icache.tagsinuse 1659.651348 # Cycle average of tags in use +system.cpu.icache.total_refs 359526375 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 24666 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14575.787521 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1656.238339 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.808710 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.808710 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 349440471 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 349440471 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 349440471 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 349440471 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 349440471 # number of overall hits -system.cpu.icache.overall_hits::total 349440471 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30457 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30457 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30457 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30457 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30457 # number of overall misses -system.cpu.icache.overall_misses::total 30457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 315232000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 315232000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 315232000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 315232000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 315232000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 315232000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 349470928 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 349470928 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 349470928 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 349470928 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 349470928 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 349470928 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10350.067308 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10350.067308 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10350.067308 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10350.067308 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10350.067308 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10350.067308 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1659.651348 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.810377 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.810377 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 359530551 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 359530551 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 359530551 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 359530551 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 359530551 # number of overall hits +system.cpu.icache.overall_hits::total 359530551 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 29629 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 29629 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 29629 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 29629 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 29629 # number of overall misses +system.cpu.icache.overall_misses::total 29629 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 243264500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 243264500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 243264500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 243264500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 243264500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 243264500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 359560180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 359560180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 359560180 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 359560180 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 359560180 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 359560180 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000082 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000082 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000082 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000082 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000082 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000082 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8210.351345 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8210.351345 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8210.351345 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8210.351345 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8210.351345 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8210.351345 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,254 +399,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 916 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 916 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 916 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 916 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 916 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 916 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29541 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 29541 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 29541 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 29541 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 29541 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 29541 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 200922000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 200922000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 200922000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 200922000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 200922000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 200922000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000085 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000085 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000085 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6801.462374 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6801.462374 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6801.462374 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6801.462374 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6801.462374 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6801.462374 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 731 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 731 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 731 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 731 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 731 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 731 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28898 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28898 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28898 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28898 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28898 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28898 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 166216000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 166216000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 166216000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 166216000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 166216000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 166216000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5751.816735 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5751.816735 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5751.816735 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 5751.816735 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5751.816735 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 5751.816735 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1533244 # number of replacements -system.cpu.dcache.tagsinuse 4094.802366 # Cycle average of tags in use -system.cpu.dcache.total_refs 977260435 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537340 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 635.682695 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 300664000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.802366 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999708 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 701107300 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 701107300 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276115713 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276115713 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 12426 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 12426 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11711 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11711 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 977223013 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 977223013 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 977223013 # number of overall hits -system.cpu.dcache.overall_hits::total 977223013 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2133926 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2133926 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 819965 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 819965 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2953891 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2953891 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2953891 # number of overall misses -system.cpu.dcache.overall_misses::total 2953891 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80611211500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80611211500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33925562500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33925562500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 304000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114536774000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114536774000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114536774000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114536774000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 703241226 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 703241226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1533081 # number of replacements +system.cpu.dcache.tagsinuse 4094.855996 # Cycle average of tags in use +system.cpu.dcache.total_refs 980345028 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537177 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 637.756763 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 283497000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.855996 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999721 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999721 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 704193068 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 704193068 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276118274 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276118274 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11579 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11579 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10994 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10994 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 980311342 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 980311342 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 980311342 # number of overall hits +system.cpu.dcache.overall_hits::total 980311342 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2282979 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2282979 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 817404 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 817404 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3100383 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3100383 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3100383 # number of overall misses +system.cpu.dcache.overall_misses::total 3100383 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 77215847500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 77215847500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27888772000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27888772000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105104619500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105104619500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105104619500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105104619500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 706476047 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 706476047 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12437 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12437 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11711 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11711 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 980176904 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 980176904 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 980176904 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 980176904 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003034 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003034 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002961 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002961 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000884 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000884 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003014 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003014 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003014 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37776.010743 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37776.010743 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41374.403176 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41374.403176 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 27636.363636 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 27636.363636 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38774.881673 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38774.881673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38774.881673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38774.881673 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11582 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11582 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10994 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10994 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 983411725 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 983411725 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 983411725 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 983411725 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003232 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003232 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002952 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002952 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000259 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000259 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003153 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003153 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33822.408134 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33822.408134 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34118.712411 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34118.712411 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33900.527612 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33900.527612 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 58500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 52500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108418 # number of writebacks -system.cpu.dcache.writebacks::total 108418 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 669125 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 669125 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743038 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 743038 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 11 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 11 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1412163 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1412163 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1412163 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1412163 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464801 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464801 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76927 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76927 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541728 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541728 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541728 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541728 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50340349002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50340349002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2506118000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2506118000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52846467002 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52846467002 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52846467002 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52846467002 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002083 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002083 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001573 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001573 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34366.681209 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34366.681209 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32577.872529 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32577.872529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34277.425721 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34277.425721 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34277.425721 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34277.425721 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 108430 # number of writebacks +system.cpu.dcache.writebacks::total 108430 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 818362 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 818362 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 740610 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 740610 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1558972 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1558972 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1558972 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1558972 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464617 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464617 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76794 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76794 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541411 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541411 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541411 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541411 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50261586500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50261586500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2476957500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2476957500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52738544000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52738544000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52738544000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52738544000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002073 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002073 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001567 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001567 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001567 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001567 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34317.221840 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34317.221840 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32254.570670 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32254.570670 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34214.459349 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34214.459349 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34214.459349 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34214.459349 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480210 # number of replacements -system.cpu.l2cache.tagsinuse 32693.720569 # Cycle average of tags in use -system.cpu.l2cache.total_refs 84475 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512954 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.055834 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480118 # number of replacements +system.cpu.l2cache.tagsinuse 32698.465426 # Cycle average of tags in use +system.cpu.l2cache.total_refs 83907 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1512862 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.055462 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3140.945883 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 59.138585 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29493.636100 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.095854 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001805 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.900074 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997733 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21968 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 54011 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 75979 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 108418 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 108418 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 3079.828905 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 55.596030 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29563.040491 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.093989 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001697 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.902192 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997878 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 21536 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53875 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 75411 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 108430 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 108430 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 6463 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6463 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21968 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 60474 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 82442 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21968 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 60474 # number of overall hits -system.cpu.l2cache.overall_hits::total 82442 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3186 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1410789 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1413975 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4385 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4385 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66077 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66077 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3186 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1476866 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1480052 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3186 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1476866 # number of overall misses -system.cpu.l2cache.overall_misses::total 1480052 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 112892000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48800392000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 48913284000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2274621500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2274621500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 112892000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 51075013500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 51187905500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 112892000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 51075013500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 51187905500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 25154 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1464800 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1489954 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 108418 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 108418 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4388 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4388 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 72540 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 72540 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 25154 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1537340 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1562494 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 25154 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1537340 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1562494 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.126660 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.963127 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.949006 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999316 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999316 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910904 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.910904 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.126660 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.960663 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.947237 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.126660 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.960663 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.947237 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35433.772756 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34590.850935 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34592.750225 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34423.801020 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34423.801020 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35433.772756 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34583.376894 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34585.207479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35433.772756 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34583.376894 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34585.207479 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 6481 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 6481 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 21536 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 60356 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 81892 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 21536 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 60356 # number of overall hits +system.cpu.l2cache.overall_hits::total 81892 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3130 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1410741 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1413871 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4230 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4230 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66081 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66081 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3130 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1476822 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1479952 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3130 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1476822 # number of overall misses +system.cpu.l2cache.overall_misses::total 1479952 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 111250000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48742266500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 48853516500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2253271500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2253271500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 111250000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 50995538000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 51106788000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 111250000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 50995538000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 51106788000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 24666 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1464616 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1489282 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 108430 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 108430 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4233 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4233 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 72562 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 72562 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 24666 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1537178 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1561844 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 24666 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1537178 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1561844 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.126895 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.963216 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.949364 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999291 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999291 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910683 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.910683 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.126895 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.960736 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.947567 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.126895 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.960736 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.947567 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35543.130990 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34550.825772 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34553.022518 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34098.628955 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34098.628955 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35543.130990 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34530.592042 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34532.733494 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35543.130990 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34530.592042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34532.733494 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -657,67 +657,67 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks system.cpu.l2cache.writebacks::total 66099 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3177 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410766 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1413943 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4385 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4385 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66077 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66077 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3177 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1476843 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1480020 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3177 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1476843 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1480020 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 102667500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44229330500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44331998000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 135941000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 135941000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2049093500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2049093500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 102667500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46278424000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46381091500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 102667500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46278424000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46381091500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.126302 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963112 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.948984 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999316 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999316 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910904 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910904 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.126302 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960648 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.947216 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.126302 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960648 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.947216 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32315.864023 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31351.287527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31353.454842 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.368301 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.368301 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.692071 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.692071 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32315.864023 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31336.048585 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.151849 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32315.864023 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31336.048585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.151849 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 33 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 33 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 33 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3119 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410719 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1413838 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4230 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4230 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66081 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66081 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3119 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1476800 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1479919 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3119 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1476800 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1479919 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 101115000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44173599500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44274714500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 131130000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 131130000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2049298500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2049298500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101115000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46222898000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46324013000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101115000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46222898000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46324013000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.126449 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.949342 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999291 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999291 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910683 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910683 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.126449 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960722 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.947546 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.126449 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960722 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.947546 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32419.044566 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31312.826651 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31315.267025 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.917193 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.917193 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32419.044566 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31299.362134 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31301.721919 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32419.044566 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31299.362134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31301.721919 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- -- cgit v1.2.3