From c49e739352b6d6bd665c78c560602d0cff1e6a1a Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 5 Jun 2012 01:23:16 -0400 Subject: all: Update stats for memory per master and total fix. --- .../ref/alpha/tru64/inorder-timing/config.ini | 6 +- .../ref/alpha/tru64/inorder-timing/simout | 6 +- .../ref/alpha/tru64/inorder-timing/stats.txt | 87 ++++++++++++++++++---- 3 files changed, 77 insertions(+), 22 deletions(-) (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing') diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 558bb295e..738c09057 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index 32687c68b..91ee744be 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:25:13 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index bbfd1b81d..0593fb6f2 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.047233 # Nu sim_ticks 47232621500 # Number of ticks simulated final_tick 47232621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62283 # Simulator instruction rate (inst/s) -host_op_rate 62283 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33300358 # Simulator tick rate (ticks/s) -host_mem_usage 223148 # Number of bytes of host memory used -host_seconds 1418.38 # Real time elapsed on the host +host_inst_rate 102058 # Simulator instruction rate (inst/s) +host_op_rate 102058 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54566702 # Simulator tick rate (ticks/s) +host_mem_usage 223484 # Number of bytes of host memory used +host_seconds 865.59 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11167232 # Number of bytes read from this memory -system.physmem.bytes_inst_read 602240 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7713024 # Number of bytes written to this memory -system.physmem.num_reads 174488 # Number of read requests responded to by this memory -system.physmem.num_writes 120516 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 236430493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 12750510 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 163298664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 399729158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 602240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10564992 # Number of bytes read from this memory +system.physmem.bytes_read::total 11167232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 602240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 602240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7713024 # Number of bytes written to this memory +system.physmem.bytes_written::total 7713024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165078 # Number of read requests responded to by this memory +system.physmem.num_reads::total 174488 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120516 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120516 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 12750510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 223679984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 236430493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 12750510 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 12750510 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 163298664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 163298664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 163298664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 12750510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 223679984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 399729158 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -156,11 +169,17 @@ system.cpu.icache.demand_accesses::total 12477840 # nu system.cpu.icache.overall_accesses::cpu.inst 12477840 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 12477840 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009478 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009478 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.009478 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009478 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009478 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009478 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17668.535383 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17668.535383 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17668.535383 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17668.535383 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 1485500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,11 +207,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 1366128500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1366128500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 1366128500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007001 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15638.633866 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15638.633866 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15638.633866 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15638.633866 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements system.cpu.dcache.tagsinuse 4073.126583 # Cycle average of tags in use @@ -236,13 +261,21 @@ system.cpu.dcache.demand_accesses::total 34890015 # nu system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004744 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004744 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045700 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.021898 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021898 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.021898 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021898 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43236.445110 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 43236.445110 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52900.510754 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52900.510754 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51683.893332 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51683.893332 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 6329431500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,13 +311,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 9343358000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9343358000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 9343358000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34375.170734 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34375.170734 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.713888 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50525.713888 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45723.000582 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45723.000582 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 148111 # number of replacements system.cpu.l2cache.tagsinuse 18671.690365 # Cycle average of tags in use @@ -349,18 +390,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 204347 system.cpu.l2cache.overall_accesses::total 291703 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.107720 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554303 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.290591 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.914655 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.914655 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.107720 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.807832 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.598170 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.107720 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.807832 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.598170 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.184910 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52204.508905 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52222.387643 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.547529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52124.547529 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52148.652056 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52148.652056 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,18 +444,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606216500 system.cpu.l2cache.overall_mshr_miss_latency::total 6983345000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554303 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.290591 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.914655 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.914655 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.598170 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.598170 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40077.417641 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.244803 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.948823 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.931559 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40020.931559 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40021.921278 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40021.921278 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- -- cgit v1.2.3