From f3585c841e964c98911784a187fc4f081a02a0a6 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 24 Jan 2014 15:29:33 -0600 Subject: stats: update stats for cache occupancy and clock domain changes --- .../ref/alpha/tru64/inorder-timing/config.ini | 9 +++++- .../ref/alpha/tru64/inorder-timing/simerr | 1 - .../ref/alpha/tru64/inorder-timing/simout | 8 ++--- .../ref/alpha/tru64/inorder-timing/stats.txt | 37 +++++++++++++++++++--- 4 files changed, 44 insertions(+), 11 deletions(-) (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing') diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index d10bd65d5..20b5204d0 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -120,6 +120,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -136,6 +137,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -158,6 +160,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -174,6 +177,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -183,6 +187,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -204,6 +209,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -220,6 +226,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -246,7 +253,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index f56fe9b31..46359a0c9 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 09:55:43 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:16:43 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 43769191000 because target called exit() +Exiting @ tick 43690025000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index fc01eaffa..391c7c37b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.043690 # Nu sim_ticks 43690025000 # Number of ticks simulated final_tick 43690025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91247 # Simulator instruction rate (inst/s) -host_op_rate 91247 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45127446 # Simulator tick rate (ticks/s) -host_mem_usage 283120 # Number of bytes of host memory used -host_seconds 968.15 # Real time elapsed on the host +host_inst_rate 133116 # Simulator instruction rate (inst/s) +host_op_rate 133116 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65834414 # Simulator tick rate (ticks/s) +host_mem_usage 238716 # Number of bytes of host memory used +host_seconds 663.64 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory system.physmem.bytes_read::total 10592960 # Number of bytes read from this memory @@ -331,6 +333,7 @@ system.membus.reqLayer0.occupancy 1218631000 # La system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) system.membus.respLayer1.occupancy 1521663500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 18742723 # Number of BP lookups system.cpu.branchPred.condPredicted 12318363 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect @@ -442,6 +445,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1906.431852 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.930875 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.930875 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2046 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1090 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 24821911 # Number of tag accesses +system.cpu.icache.tags.data_accesses 24821911 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 12250505 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 12250505 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 12250505 # number of demand (read+write) hits @@ -550,6 +561,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.826966 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061272 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.054475 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.942712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32060 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17071 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13589 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 108 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978394 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3980332 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3980332 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 33055 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 112369 # number of ReadReq hits @@ -684,6 +704,13 @@ system.cpu.dcache.tags.warmup_cycle 297515000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4076.382661 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995211 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995211 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 922 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3118 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 69984376 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 69984376 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 20180292 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20180292 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 13574591 # number of WriteReq hits -- cgit v1.2.3