From 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Fri, 6 Nov 2015 03:26:50 -0500 Subject: stats: Update stats to match cache changes --- .../ref/alpha/tru64/minor-timing/stats.txt | 1031 ++++++++++---------- 1 file changed, 518 insertions(+), 513 deletions(-) (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt') diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 15844baba..e086bc978 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.059549 # Number of seconds simulated -sim_ticks 59549031000 # Number of ticks simulated -final_tick 59549031000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.059474 # Number of seconds simulated +sim_ticks 59473862000 # Number of ticks simulated +final_tick 59473862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 320796 # Simulator instruction rate (inst/s) -host_op_rate 320796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216005540 # Simulator tick rate (ticks/s) -host_mem_usage 307628 # Number of bytes of host memory used -host_seconds 275.68 # Real time elapsed on the host +host_inst_rate 342067 # Simulator instruction rate (inst/s) +host_op_rate 342067 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 230037089 # Simulator tick rate (ticks/s) +host_mem_usage 307480 # Number of bytes of host memory used +host_seconds 258.54 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 500352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10147264 # Number of bytes read from this memory -system.physmem.bytes_read::total 10647616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 500352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 500352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7320640 # Number of bytes written to this memory -system.physmem.bytes_written::total 7320640 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7818 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158551 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166369 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114385 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114385 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8402353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 170401832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 178804186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8402353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8402353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122934662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122934662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122934662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8402353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 170401832 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 301738848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166369 # Number of read requests accepted -system.physmem.writeReqs 114385 # Number of write requests accepted -system.physmem.readBursts 166369 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114385 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10647296 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 7318592 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10647616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7320640 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 432448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10149376 # Number of bytes read from this memory +system.physmem.bytes_read::total 10581824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 432448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 432448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7325760 # Number of bytes written to this memory +system.physmem.bytes_written::total 7325760 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158584 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165341 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114465 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114465 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7271228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 170652715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 177923942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7271228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7271228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 123176127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 123176127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 123176127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7271228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 170652715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 301100070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165341 # Number of read requests accepted +system.physmem.writeReqs 114465 # Number of write requests accepted +system.physmem.readBursts 165341 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114465 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10581376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 7323904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10581824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7325760 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10447 # Per bank write bursts -system.physmem.perBankRdBursts::1 10506 # Per bank write bursts -system.physmem.perBankRdBursts::2 10283 # Per bank write bursts -system.physmem.perBankRdBursts::3 10092 # Per bank write bursts -system.physmem.perBankRdBursts::4 10413 # Per bank write bursts -system.physmem.perBankRdBursts::5 10414 # Per bank write bursts -system.physmem.perBankRdBursts::6 9828 # Per bank write bursts -system.physmem.perBankRdBursts::7 10274 # Per bank write bursts -system.physmem.perBankRdBursts::8 10580 # Per bank write bursts -system.physmem.perBankRdBursts::9 10645 # Per bank write bursts -system.physmem.perBankRdBursts::10 10558 # Per bank write bursts -system.physmem.perBankRdBursts::11 10261 # Per bank write bursts -system.physmem.perBankRdBursts::12 10296 # Per bank write bursts -system.physmem.perBankRdBursts::13 10620 # Per bank write bursts -system.physmem.perBankRdBursts::14 10515 # Per bank write bursts -system.physmem.perBankRdBursts::15 10632 # Per bank write bursts -system.physmem.perBankWrBursts::0 7162 # Per bank write bursts -system.physmem.perBankWrBursts::1 7273 # Per bank write bursts -system.physmem.perBankWrBursts::2 7295 # Per bank write bursts -system.physmem.perBankWrBursts::3 7000 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 14983 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10312 # Per bank write bursts +system.physmem.perBankRdBursts::1 10359 # Per bank write bursts +system.physmem.perBankRdBursts::2 10206 # Per bank write bursts +system.physmem.perBankRdBursts::3 10057 # Per bank write bursts +system.physmem.perBankRdBursts::4 10348 # Per bank write bursts +system.physmem.perBankRdBursts::5 10339 # Per bank write bursts +system.physmem.perBankRdBursts::6 9776 # Per bank write bursts +system.physmem.perBankRdBursts::7 10207 # Per bank write bursts +system.physmem.perBankRdBursts::8 10534 # Per bank write bursts +system.physmem.perBankRdBursts::9 10607 # Per bank write bursts +system.physmem.perBankRdBursts::10 10498 # Per bank write bursts +system.physmem.perBankRdBursts::11 10228 # Per bank write bursts +system.physmem.perBankRdBursts::12 10274 # Per bank write bursts +system.physmem.perBankRdBursts::13 10561 # Per bank write bursts +system.physmem.perBankRdBursts::14 10464 # Per bank write bursts +system.physmem.perBankRdBursts::15 10564 # Per bank write bursts +system.physmem.perBankWrBursts::0 7163 # Per bank write bursts +system.physmem.perBankWrBursts::1 7274 # Per bank write bursts +system.physmem.perBankWrBursts::2 7296 # Per bank write bursts +system.physmem.perBankWrBursts::3 7002 # Per bank write bursts system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7181 # Per bank write bursts +system.physmem.perBankWrBursts::5 7187 # Per bank write bursts system.physmem.perBankWrBursts::6 6833 # Per bank write bursts -system.physmem.perBankWrBursts::7 7084 # Per bank write bursts -system.physmem.perBankWrBursts::8 7224 # Per bank write bursts -system.physmem.perBankWrBursts::9 6994 # Per bank write bursts -system.physmem.perBankWrBursts::10 7113 # Per bank write bursts -system.physmem.perBankWrBursts::11 6992 # Per bank write bursts -system.physmem.perBankWrBursts::12 6991 # Per bank write bursts -system.physmem.perBankWrBursts::13 7295 # Per bank write bursts -system.physmem.perBankWrBursts::14 7307 # Per bank write bursts +system.physmem.perBankWrBursts::7 7099 # Per bank write bursts +system.physmem.perBankWrBursts::8 7225 # Per bank write bursts +system.physmem.perBankWrBursts::9 7000 # Per bank write bursts +system.physmem.perBankWrBursts::10 7115 # Per bank write bursts +system.physmem.perBankWrBursts::11 7034 # Per bank write bursts +system.physmem.perBankWrBursts::12 6992 # Per bank write bursts +system.physmem.perBankWrBursts::13 7299 # Per bank write bursts +system.physmem.perBankWrBursts::14 7308 # Per bank write bursts system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 59549007000 # Total gap between requests +system.physmem.totGap 59473838000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166369 # Read request sizes (log2) +system.physmem.readPktSize::6 165341 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114385 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1588 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114465 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1560 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,122 +193,120 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54768 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 328.014023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.067660 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.383666 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19491 35.59% 35.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11850 21.64% 57.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5663 10.34% 67.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3680 6.72% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2902 5.30% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2048 3.74% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1635 2.99% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1469 2.68% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6030 11.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54768 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7038 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.634839 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.413145 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7035 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 54714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.237051 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.297949 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.344141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19597 35.82% 35.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11811 21.59% 57.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5572 10.18% 67.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3684 6.73% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2893 5.29% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2049 3.74% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1621 2.96% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1502 2.75% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5985 10.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54714 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7041 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.479761 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 336.363256 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7038 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7038 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7038 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.247940 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.232365 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.745442 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6264 89.00% 89.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 17 0.24% 89.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 601 8.54% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 122 1.73% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 23 0.33% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 6 0.09% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7041 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7041 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.252805 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.237164 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.745060 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6251 88.78% 88.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 16 0.23% 89.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 606 8.61% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 134 1.90% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 28 0.40% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.06% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7038 # Writes before turning the bus around for reads -system.physmem.totQLat 2001235750 # Total ticks spent queuing -system.physmem.totMemAccLat 5120560750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831820000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12029.26 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7041 # Writes before turning the bus around for reads +system.physmem.totQLat 1980163000 # Total ticks spent queuing +system.physmem.totMemAccLat 5080175500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 826670000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11976.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30779.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 178.80 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 178.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30726.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 177.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 123.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 177.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 123.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.36 # Data bus utilization in percentage -system.physmem.busUtilRead 1.40 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.35 # Data bus utilization in percentage +system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing -system.physmem.readRowHits 144462 # Number of row buffer hits during reads -system.physmem.writeRowHits 81475 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.23 # Row buffer hit rate for writes -system.physmem.avgGap 212103.86 # Average gap between requests -system.physmem.pageHitRate 80.48 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 199614240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108916500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 641355000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 368899920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3888958320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12587581890 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24683289750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42478615620 # Total energy per rank (pJ) -system.physmem_0.averagePower 713.426150 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40913813750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1988220000 # Time in different power states +system.physmem.avgWrQLen 23.98 # Average write queue length when enqueuing +system.physmem.readRowHits 143867 # Number of row buffer hits during reads +system.physmem.writeRowHits 81182 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.92 # Row buffer hit rate for writes +system.physmem.avgGap 212553.83 # Average gap between requests +system.physmem.pageHitRate 80.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199175760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108677250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 636448800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 369204480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3884381280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12421725570 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24786732000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42406345140 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.051581 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 41087166750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1985880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16639693750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16398707250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214137000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116840625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 655777200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371764080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3888958320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13157757450 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24183135750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42588370425 # Total energy per rank (pJ) -system.physmem_1.averagePower 715.269477 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40075806250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1988220000 # Time in different power states +system.physmem_1.actEnergy 214341120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116952000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 652938000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 372237120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3884381280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13062187260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24224923500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42527960280 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.096508 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40147172500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1985880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17478332750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17338598750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14666095 # Number of BP lookups -system.cpu.branchPred.condPredicted 9488989 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 386100 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9897774 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6385513 # Number of BTB hits +system.cpu.branchPred.lookups 14666171 # Number of BP lookups +system.cpu.branchPred.condPredicted 9489023 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 386095 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9897790 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6385525 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.514637 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1708089 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84886 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 64.514654 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1708105 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84877 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20569916 # DTB read hits -system.cpu.dtb.read_misses 97322 # DTB read misses +system.cpu.dtb.read_hits 20569903 # DTB read hits +system.cpu.dtb.read_misses 97320 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20667238 # DTB read accesses -system.cpu.dtb.write_hits 14665322 # DTB write hits +system.cpu.dtb.read_accesses 20667223 # DTB read accesses +system.cpu.dtb.write_hits 14665328 # DTB write hits system.cpu.dtb.write_misses 9407 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674729 # DTB write accesses -system.cpu.dtb.data_hits 35235238 # DTB hits -system.cpu.dtb.data_misses 106729 # DTB misses +system.cpu.dtb.write_accesses 14674735 # DTB write accesses +system.cpu.dtb.data_hits 35235231 # DTB hits +system.cpu.dtb.data_misses 106727 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35341967 # DTB accesses -system.cpu.itb.fetch_hits 25606453 # ITB hits -system.cpu.itb.fetch_misses 5227 # ITB misses +system.cpu.dtb.data_accesses 35341958 # DTB accesses +system.cpu.itb.fetch_hits 25606544 # ITB hits +system.cpu.itb.fetch_misses 5228 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25611680 # ITB accesses +system.cpu.itb.fetch_accesses 25611772 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -322,65 +320,65 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 119098062 # number of cpu cycles simulated +system.cpu.numCycles 118947724 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1106110 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1106117 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.346683 # CPI: cycles per instruction -system.cpu.ipc 0.742565 # IPC: instructions per cycle -system.cpu.tickCycles 91473495 # Number of cycles that the object actually ticked -system.cpu.idleCycles 27624567 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.344983 # CPI: cycles per instruction +system.cpu.ipc 0.743504 # IPC: instructions per cycle +system.cpu.tickCycles 91473408 # Number of cycles that the object actually ticked +system.cpu.idleCycles 27474316 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 200766 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.715334 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34616231 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4070.683377 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34616213 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 204862 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.973411 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.973324 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 687575500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.715334 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993827 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993827 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.683377 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993819 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993819 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 686 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3360 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3361 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70176386 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70176386 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20282965 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20282965 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333266 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333266 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34616231 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34616231 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34616231 # number of overall hits -system.cpu.dcache.overall_hits::total 34616231 # number of overall hits +system.cpu.dcache.tags.tag_accesses 70176360 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70176360 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20282952 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20282952 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333261 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333261 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34616213 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34616213 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34616213 # number of overall hits +system.cpu.dcache.overall_hits::total 34616213 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 89420 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 89420 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280111 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280111 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 369531 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369531 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369531 # number of overall misses -system.cpu.dcache.overall_misses::total 369531 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4765724000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4765724000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21723340000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21723340000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26489064000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26489064000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26489064000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26489064000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20372385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 280116 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280116 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 369536 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369536 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369536 # number of overall misses +system.cpu.dcache.overall_misses::total 369536 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4768019500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4768019500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21708920500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21708920500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26476940000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26476940000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26476940000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26476940000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20372372 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20372372 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34985762 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34985762 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34985762 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34985762 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34985749 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34985749 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34985749 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34985749 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004389 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004389 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses @@ -389,14 +387,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.010562 system.cpu.dcache.demand_miss_rate::total 0.010562 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.010562 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.010562 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53295.951689 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53295.951689 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77552.613071 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77552.613071 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71682.927819 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71682.927819 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71682.927819 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71682.927819 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53321.622679 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53321.622679 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77499.751889 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77499.751889 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71649.149203 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71649.149203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71649.149203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71649.149203 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,16 +403,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168453 # number of writebacks -system.cpu.dcache.writebacks::total 168453 # number of writebacks +system.cpu.dcache.writebacks::writebacks 168423 # number of writebacks +system.cpu.dcache.writebacks::total 168423 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28115 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 28115 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136554 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136554 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 164669 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164669 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 164669 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164669 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136559 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136559 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 164674 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164674 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 164674 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164674 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61305 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61305 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143557 # number of WriteReq MSHR misses @@ -423,14 +421,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204862 system.cpu.dcache.demand_mshr_misses::total 204862 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204862 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204862 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2678183500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2678183500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10981560500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10981560500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13659744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13659744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13659744000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13659744000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2680071500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2680071500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10970928000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10970928000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13650999500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13650999500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13650999500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13650999500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -439,69 +437,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43686.216459 # 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Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42309465500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1932.369225 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.943540 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.943540 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 152856 # number of replacements +system.cpu.icache.tags.tagsinuse 1932.301021 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25451639 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 154904 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 164.305886 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42254913500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1932.301021 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.943506 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.943506 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1041 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51367805 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51367805 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25451553 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25451553 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25451553 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25451553 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25451553 # number of overall hits -system.cpu.icache.overall_hits::total 25451553 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 154900 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 154900 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 154900 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 154900 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 154900 # number of overall misses -system.cpu.icache.overall_misses::total 154900 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2550963000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2550963000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2550963000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2550963000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2550963000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2550963000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25606453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25606453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25606453 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25606453 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25606453 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25606453 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 51367992 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51367992 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25451639 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25451639 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25451639 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25451639 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25451639 # number of overall hits +system.cpu.icache.overall_hits::total 25451639 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 154905 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 154905 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 154905 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 154905 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 154905 # number of overall misses +system.cpu.icache.overall_misses::total 154905 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2479923000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2479923000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2479923000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2479923000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2479923000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2479923000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25606544 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25606544 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25606544 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25606544 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25606544 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25606544 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006049 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.006049 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.006049 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.006049 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.006049 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.006049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16468.450613 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16468.450613 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16468.450613 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16468.450613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16468.450613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16468.450613 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16009.315387 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16009.315387 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16009.315387 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16009.315387 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16009.315387 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16009.315387 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,129 +508,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154900 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 154900 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 154900 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 154900 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 154900 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 154900 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2396064000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2396064000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2396064000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2396064000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2396064000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2396064000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 152856 # number of writebacks +system.cpu.icache.writebacks::total 152856 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154905 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 154905 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 154905 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 154905 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 154905 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 154905 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2325019000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2325019000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2325019000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2325019000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2325019000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2325019000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006049 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006049 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15468.457069 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15468.457069 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15468.457069 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15468.457069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15468.457069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15468.457069 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15009.321842 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15009.321842 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15009.321842 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15009.321842 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15009.321842 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15009.321842 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132445 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30425.579826 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 402950 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164521 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.449231 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 133370 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30430.165732 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 403981 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 165480 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.441268 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 25961.899693 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2481.819774 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1981.860360 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.792294 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075739 # 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mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.050478 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451341 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451341 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.050478 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773941 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.462445 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.050478 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773941 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.462445 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71241.748292 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71241.748292 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69204.949482 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69204.949482 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70689.670751 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70689.670751 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69204.949482 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71145.404318 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71054.207489 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69204.949482 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71145.404318 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71054.207489 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911708 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911708 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043627 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451863 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451863 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.774102 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.459581 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.774102 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.459581 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71159.898535 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71159.898535 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69449.985203 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69449.985203 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70675.968377 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70675.968377 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69449.985203 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71075.366998 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71008.932999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69449.985203 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71075.366998 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71008.932999 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 713379 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 353617 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 713389 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 353622 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4025 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4025 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4036 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4036 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 216203 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 282838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 203224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 216208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 282888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 152856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143558 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 154900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 154905 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 61304 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462650 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462665 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1073140 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9913536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23892160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33805696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 132445 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 845824 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004759 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.068819 # Request fanout histogram +system.cpu.toL2Bus.pkt_count::total 1073155 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19696640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23890240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43586880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 133370 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 493137 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008184 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.090096 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 841799 99.52% 99.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4025 0.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 489101 99.18% 99.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4036 0.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 845824 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 525142500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 232349997 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 493137 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 677973500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 232357497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307296493 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307299487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 35487 # Transaction distribution -system.membus.trans_dist::Writeback 114385 # Transaction distribution -system.membus.trans_dist::CleanEvict 16125 # Transaction distribution -system.membus.trans_dist::ReadExReq 130882 # Transaction distribution -system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35487 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463248 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 463248 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17968256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17968256 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 34458 # Transaction distribution +system.membus.trans_dist::WritebackDirty 114465 # Transaction distribution +system.membus.trans_dist::CleanEvict 14983 # Transaction distribution +system.membus.trans_dist::ReadExReq 130883 # Transaction distribution +system.membus.trans_dist::ReadExResp 130883 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34458 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 460130 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17907584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17907584 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 296879 # Request fanout histogram +system.membus.snoop_fanout::samples 294789 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 296879 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 294789 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 296879 # Request fanout histogram -system.membus.reqLayer0.occupancy 824874000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 294789 # Request fanout histogram +system.membus.reqLayer0.occupancy 822943500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 878418750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 872924250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- -- cgit v1.2.3