From 2823982a3cbd60a1b21db1a73b78440468df158a Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Tue, 26 Nov 2013 17:05:25 -0600 Subject: stats: updates due to changes to ticksToCycles() --- .../50.vortex/ref/arm/linux/o3-timing/config.ini | 77 +- .../se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1698 ++++++++++---------- 2 files changed, 924 insertions(+), 851 deletions(-) (limited to 'tests/long/se/50.vortex/ref/arm') diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index a8a1f643c..9b769867b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 1084e1661..df6074257 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026816 # Number of seconds simulated -sim_ticks 26816405500 # Number of ticks simulated -final_tick 26816405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026810 # Number of seconds simulated +sim_ticks 26810051000 # Number of ticks simulated +final_tick 26810051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109329 # Simulator instruction rate (inst/s) -host_op_rate 155152 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41346943 # Simulator tick rate (ticks/s) -host_mem_usage 283460 # Number of bytes of host memory used -host_seconds 648.57 # Real time elapsed on the host +host_inst_rate 86453 # Simulator instruction rate (inst/s) +host_op_rate 122688 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32687774 # Simulator tick rate (ticks/s) +host_mem_usage 303000 # Number of bytes of host memory used +host_seconds 820.19 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942848 # Number of bytes read from this memory -system.physmem.bytes_read::total 8241280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372096 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124107 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128770 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83939 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83939 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11128710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296193612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307322322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11128710 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11128710 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200328713 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200328713 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200328713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11128710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296193612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 507651035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128770 # Number of read requests accepted -system.physmem.writeReqs 83939 # Number of write requests accepted -system.physmem.readBursts 128770 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83939 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8241152 # Total number of bytes read from DRAM +system.physmem.bytes_read::cpu.inst 299136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory +system.physmem.bytes_read::total 8242368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 299136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 299136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372608 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4674 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124113 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128787 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83947 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83947 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11157607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296278138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307435745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11157607 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11157607 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200395292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200395292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200395292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11157607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296278138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 507831037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128788 # Number of read requests accepted +system.physmem.writeReqs 83947 # Number of write requests accepted +system.physmem.readBursts 128788 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83947 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8242304 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371520 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8241280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372096 # Total written bytes from the system interface side +system.physmem.bytesWritten 5371392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8242432 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372608 # Total written bytes from the system interface side system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 318 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8144 # Per bank write bursts -system.physmem.perBankRdBursts::1 8386 # Per bank write bursts -system.physmem.perBankRdBursts::2 8247 # Per bank write bursts -system.physmem.perBankRdBursts::3 8164 # Per bank write bursts -system.physmem.perBankRdBursts::4 8296 # Per bank write bursts -system.physmem.perBankRdBursts::5 8451 # Per bank write bursts -system.physmem.perBankRdBursts::6 8094 # Per bank write bursts -system.physmem.perBankRdBursts::7 7961 # Per bank write bursts -system.physmem.perBankRdBursts::8 8061 # Per bank write bursts -system.physmem.perBankRdBursts::9 7610 # Per bank write bursts -system.physmem.perBankRdBursts::10 7787 # Per bank write bursts -system.physmem.perBankRdBursts::11 7813 # Per bank write bursts -system.physmem.perBankRdBursts::12 7882 # Per bank write bursts -system.physmem.perBankRdBursts::13 7886 # Per bank write bursts -system.physmem.perBankRdBursts::14 7979 # Per bank write bursts -system.physmem.perBankRdBursts::15 8007 # Per bank write bursts -system.physmem.perBankWrBursts::0 5180 # Per bank write bursts -system.physmem.perBankWrBursts::1 5376 # Per bank write bursts -system.physmem.perBankWrBursts::2 5287 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 308 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8141 # Per bank write bursts +system.physmem.perBankRdBursts::1 8391 # Per bank write bursts +system.physmem.perBankRdBursts::2 8249 # Per bank write bursts +system.physmem.perBankRdBursts::3 8162 # Per bank write bursts +system.physmem.perBankRdBursts::4 8307 # Per bank write bursts +system.physmem.perBankRdBursts::5 8450 # Per bank write bursts +system.physmem.perBankRdBursts::6 8088 # Per bank write bursts +system.physmem.perBankRdBursts::7 7966 # Per bank write bursts +system.physmem.perBankRdBursts::8 8060 # Per bank write bursts +system.physmem.perBankRdBursts::9 7616 # Per bank write bursts +system.physmem.perBankRdBursts::10 7784 # Per bank write bursts +system.physmem.perBankRdBursts::11 7815 # Per bank write bursts +system.physmem.perBankRdBursts::12 7881 # Per bank write bursts +system.physmem.perBankRdBursts::13 7887 # Per bank write bursts +system.physmem.perBankRdBursts::14 7977 # Per bank write bursts +system.physmem.perBankRdBursts::15 8012 # Per bank write bursts +system.physmem.perBankWrBursts::0 5178 # Per bank write bursts +system.physmem.perBankWrBursts::1 5375 # Per bank write bursts +system.physmem.perBankWrBursts::2 5292 # Per bank write bursts system.physmem.perBankWrBursts::3 5157 # Per bank write bursts -system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::4 5267 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5205 # Per bank write bursts -system.physmem.perBankWrBursts::7 5049 # Per bank write bursts -system.physmem.perBankWrBursts::8 5030 # Per bank write bursts +system.physmem.perBankWrBursts::6 5206 # Per bank write bursts +system.physmem.perBankWrBursts::7 5050 # Per bank write bursts +system.physmem.perBankWrBursts::8 5028 # Per bank write bursts system.physmem.perBankWrBursts::9 5090 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts -system.physmem.perBankWrBursts::11 5144 # Per bank write bursts +system.physmem.perBankWrBursts::10 5248 # Per bank write bursts +system.physmem.perBankWrBursts::11 5142 # Per bank write bursts system.physmem.perBankWrBursts::12 5342 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5223 # Per bank write bursts +system.physmem.perBankWrBursts::15 5222 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26816294000 # Total gap between requests +system.physmem.totGap 26810034000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128770 # Read request sizes (log2) +system.physmem.readPktSize::6 128788 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83939 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 72833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83947 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 72914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -127,31 +127,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3685 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3681 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 3679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -159,189 +159,189 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37861 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 359.431816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.292002 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 695.442994 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 15095 39.87% 39.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5646 14.91% 54.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3407 9.00% 63.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2352 6.21% 69.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1734 4.58% 74.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1565 4.13% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1073 2.83% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 929 2.45% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 665 1.76% 85.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 565 1.49% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 384 1.01% 88.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 558 1.47% 89.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 286 0.76% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 361 0.95% 91.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 176 0.46% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 218 0.58% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 133 0.35% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 117 0.31% 93.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 270 0.71% 94.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 104 0.27% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 418 1.10% 95.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 100 0.26% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 243 0.64% 96.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 38 0.10% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 144 0.38% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 38 0.10% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 86 0.23% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 54 0.14% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 16 0.04% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 43 0.11% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 22 0.06% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37958 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 358.604352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 173.758574 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 692.410978 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 15190 40.02% 40.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5700 15.02% 55.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3416 9.00% 64.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2313 6.09% 70.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1704 4.49% 74.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1539 4.05% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1108 2.92% 81.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 903 2.38% 83.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 681 1.79% 85.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 548 1.44% 87.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 355 0.94% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 578 1.52% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 299 0.79% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 386 1.02% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 183 0.48% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 223 0.59% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 117 0.31% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 252 0.66% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 118 0.31% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 257 0.68% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 108 0.28% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 421 1.11% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 88 0.23% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 246 0.65% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 43 0.11% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 122 0.32% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 43 0.11% 97.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 88 0.23% 97.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 65 0.17% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 27 0.07% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 45 0.12% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 16 0.04% 98.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::2176-2177 34 0.09% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 17 0.04% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 32 0.08% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 11 0.03% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 29 0.08% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 17 0.04% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 31 0.08% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 15 0.04% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 15 0.04% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 11 0.03% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 11 0.03% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 9 0.02% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 8 0.02% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 21 0.06% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 10 0.03% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 21 0.06% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 8 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 15 0.04% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 29 0.08% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 15 0.04% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 24 0.06% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 13 0.03% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 34 0.09% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 13 0.03% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 17 0.04% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 7 0.02% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 19 0.05% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 9 0.02% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 17 0.04% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 10 0.03% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 27 0.07% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 7 0.02% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 14 0.04% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 10 0.03% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 15 0.04% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 6 0.02% 98.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 6 0.02% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 11 0.03% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 10 0.03% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 7 0.02% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 17 0.04% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 5 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 10 0.03% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 7 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 6 0.02% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 8 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 4 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 6 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 7 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 2 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 9 0.02% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 6 0.02% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 13 0.03% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 11 0.03% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.02% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 8 0.02% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 10 0.03% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 6 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 7 0.02% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 8 0.02% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 2 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 4 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 2 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 6 0.02% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 11 0.03% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 10 0.03% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 7 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 10 0.03% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 13 0.03% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 7 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.03% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 8 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 13 0.03% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 3 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 9 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 7 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 7 0.02% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 8 0.02% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 6 0.02% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 8 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 5 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 9 0.02% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 9 0.02% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 7 0.02% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 9 0.02% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 6 0.02% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 8 0.02% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.02% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 9 0.02% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 5 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 7 0.02% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 7 0.02% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 2 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 5 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 3 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 4 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 7 0.02% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 4 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 4 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 2 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 2 0.01% 99.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 3 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 6 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.01% 99.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 4 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 3 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 4 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 3 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 5 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 2 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 3 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.01% 99.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 36 0.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37861 # Bytes accessed per row activation -system.physmem.totQLat 3024623000 # Total ticks spent queuing -system.physmem.totMemAccLat 4968016750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643840000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1299553750 # Total ticks spent accessing banks -system.physmem.avgQLat 23488.93 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 10092.21 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 35 0.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37958 # Bytes accessed per row activation +system.physmem.totQLat 3020745250 # Total ticks spent queuing +system.physmem.totMemAccLat 4967419000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643930000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1302743750 # Total ticks spent accessing banks +system.physmem.avgQLat 23455.54 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10115.57 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38581.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 307.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 200.31 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 307.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 200.33 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38571.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 307.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 200.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 307.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 200.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.97 # Data bus utilization in percentage system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.56 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.76 # Average write queue length when enqueuing -system.physmem.readRowHits 117866 # Number of row buffer hits during reads -system.physmem.writeRowHits 56971 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.73 # Average write queue length when enqueuing +system.physmem.readRowHits 117878 # Number of row buffer hits during reads +system.physmem.writeRowHits 56878 # Number of row buffer hits during writes system.physmem.readRowHitRate 91.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.87 # Row buffer hit rate for writes -system.physmem.avgGap 126070.33 # Average gap between requests -system.physmem.pageHitRate 82.20 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 11.88 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 507651035 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26514 # Transaction distribution -system.membus.trans_dist::ReadResp 26514 # Transaction distribution -system.membus.trans_dist::Writeback 83939 # Transaction distribution -system.membus.trans_dist::UpgradeReq 318 # Transaction distribution -system.membus.trans_dist::UpgradeResp 318 # Transaction distribution -system.membus.trans_dist::ReadExReq 102256 # Transaction distribution -system.membus.trans_dist::ReadExResp 102256 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342115 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342115 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13613376 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13613376 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13613376 # Total data (bytes) +system.physmem.writeRowHitRate 67.75 # Row buffer hit rate for writes +system.physmem.avgGap 126025.50 # Average gap between requests +system.physmem.pageHitRate 82.15 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.63 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 507831037 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26531 # Transaction distribution +system.membus.trans_dist::ReadResp 26530 # Transaction distribution +system.membus.trans_dist::Writeback 83947 # Transaction distribution +system.membus.trans_dist::UpgradeReq 308 # Transaction distribution +system.membus.trans_dist::UpgradeResp 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 102257 # Transaction distribution +system.membus.trans_dist::ReadExResp 102257 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342138 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614976 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13614976 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13614976 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 934803500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 934752500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1203423433 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1203686693 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) -system.cpu.branchPred.lookups 16622919 # Number of BP lookups -system.cpu.branchPred.condPredicted 12749857 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 605504 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10570940 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7775711 # Number of BTB hits +system.cpu.branchPred.lookups 16646392 # Number of BP lookups +system.cpu.branchPred.condPredicted 12773976 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 607235 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10818826 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7781096 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.557423 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1829148 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113993 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.921815 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1825486 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113411 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -385,239 +385,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53632812 # number of cpu cycles simulated +system.cpu.numCycles 53620103 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12575227 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85200235 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16622919 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9604859 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21200799 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2368859 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10684050 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 493 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11692200 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 184239 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46197272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.582993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.332808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12555863 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85327612 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16646392 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9606582 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21220606 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2386309 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10655499 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 479 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11697004 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 183631 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46184612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.586702 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.333983 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25016575 54.15% 54.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2138831 4.63% 58.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1968354 4.26% 63.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2045405 4.43% 67.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1466932 3.18% 70.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1376276 2.98% 73.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 961294 2.08% 75.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1190217 2.58% 78.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10033388 21.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24984951 54.10% 54.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2138585 4.63% 58.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1966197 4.26% 62.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2046003 4.43% 67.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1469884 3.18% 70.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1382868 2.99% 73.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 958032 2.07% 75.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1189943 2.58% 78.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10048149 21.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46197272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309939 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.588584 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14661485 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9032065 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19500717 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1369785 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1633220 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3334387 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 105402 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116870755 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 365005 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1633220 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16370455 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2587455 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1031873 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19111398 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5462871 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114984523 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 46184612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310451 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.591336 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14642918 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9005955 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19517473 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1369283 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1648983 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3334820 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 105179 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116999070 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 363013 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1648983 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16350179 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2575616 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1030832 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19130431 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5448571 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 115098604 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15960 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4602334 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 241 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115277175 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529754178 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 476504412 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2548 # Number of floating rename lookups +system.cpu.rename.IQFullEvents 17023 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4589680 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 256 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115425064 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 530260724 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 476967295 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2691 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16144503 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20627 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20613 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12986013 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29603679 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22442541 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3905979 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4383979 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111534291 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36144 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107247539 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 279427 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10792871 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25872402 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2358 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46197272 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.321512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.989577 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16292392 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20388 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20384 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12970121 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29626660 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22464166 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3855353 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4357218 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111639066 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 36000 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107318490 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 273494 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10897204 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 26020912 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46184612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.323685 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.992080 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10946962 23.70% 23.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8090791 17.51% 41.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7422192 16.07% 57.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7125519 15.42% 72.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5414632 11.72% 84.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3916527 8.48% 92.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1842332 3.99% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 865884 1.87% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 572433 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10954733 23.72% 23.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8081116 17.50% 41.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7387326 16.00% 57.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7126917 15.43% 72.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5408207 11.71% 84.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3931545 8.51% 92.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1847862 4.00% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 871002 1.89% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 575904 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46197272 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46184612 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 111334 4.52% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 1 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1349070 54.73% 59.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1004381 40.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112087 4.51% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 3 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1355242 54.58% 59.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1015813 40.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56643981 52.82% 52.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91446 0.09% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 176 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28888115 26.94% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21623814 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56685703 52.82% 52.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91410 0.09% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 203 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28899327 26.93% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21641840 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107247539 # Type of FU issued -system.cpu.iq.rate 1.999663 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2464786 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022982 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263436010 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122391385 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105557389 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 553 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 926 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 158 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109712054 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 271 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2181647 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107318490 # Type of FU issued +system.cpu.iq.rate 2.001460 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2483145 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023138 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263577666 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122600736 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105627540 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 565 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 906 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109801353 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 282 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2178214 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2296571 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6409 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29938 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1886803 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2319552 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6675 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30486 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1908428 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 637 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 694 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1633220 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1092915 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45139 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111580294 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 294739 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29603679 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22442541 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20224 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6335 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5295 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29938 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 394730 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181332 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 576062 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106214921 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28587238 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1032618 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1648983 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1092293 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45577 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111684840 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 295051 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29626660 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22464166 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20080 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6356 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5380 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30486 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 395595 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 182079 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 577674 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106281813 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28597262 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1036677 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9859 # number of nop insts executed -system.cpu.iew.exec_refs 49925863 # number of memory reference insts executed -system.cpu.iew.exec_branches 14600722 # Number of branches executed -system.cpu.iew.exec_stores 21338625 # Number of stores executed -system.cpu.iew.exec_rate 1.980409 # Inst execution rate -system.cpu.iew.wb_sent 105779922 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105557547 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53302648 # num instructions producing a value -system.cpu.iew.wb_consumers 103946447 # num instructions consuming a value +system.cpu.iew.exec_nop 9774 # number of nop insts executed +system.cpu.iew.exec_refs 49953963 # number of memory reference insts executed +system.cpu.iew.exec_branches 14606559 # Number of branches executed +system.cpu.iew.exec_stores 21356701 # Number of stores executed +system.cpu.iew.exec_rate 1.982126 # Inst execution rate +system.cpu.iew.wb_sent 105847179 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105627710 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53336530 # num instructions producing a value +system.cpu.iew.wb_consumers 104015656 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.968152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512790 # average fanout of values written-back +system.cpu.iew.wb_rate 1.969927 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512774 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10948789 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11053294 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 502113 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44564052 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.258153 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.763889 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 504169 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44535629 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.259594 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.766011 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15506218 34.80% 34.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11644493 26.13% 60.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3446423 7.73% 68.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2869378 6.44% 75.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1870309 4.20% 79.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1959985 4.40% 83.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685768 1.54% 85.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 560638 1.26% 86.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6020840 13.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15484235 34.77% 34.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11649742 26.16% 60.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3457573 7.76% 68.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2865921 6.44% 75.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1843682 4.14% 79.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1946516 4.37% 83.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 688008 1.54% 85.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 565195 1.27% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6034757 13.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44564052 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44535629 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -628,226 +628,226 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6020840 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6034757 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150099130 # The number of ROB reads -system.cpu.rob.rob_writes 224804524 # The number of ROB writes -system.cpu.timesIdled 76985 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7435540 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150161295 # The number of ROB reads +system.cpu.rob.rob_writes 225029668 # The number of ROB writes +system.cpu.timesIdled 76463 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7435491 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.756376 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.756376 # CPI: Total CPI of All Threads -system.cpu.ipc 1.322094 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.322094 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511539854 # number of integer regfile reads -system.cpu.int_regfile_writes 103334614 # number of integer regfile writes -system.cpu.fp_regfile_reads 734 # number of floating regfile reads -system.cpu.fp_regfile_writes 630 # number of floating regfile writes -system.cpu.misc_regfile_reads 49164319 # number of misc regfile reads +system.cpu.cpi 0.756197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.756197 # CPI: Total CPI of All Threads +system.cpu.ipc 1.322408 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.322408 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511842322 # number of integer regfile reads +system.cpu.int_regfile_writes 103400028 # number of integer regfile writes +system.cpu.fp_regfile_reads 836 # number of floating regfile reads +system.cpu.fp_regfile_writes 732 # number of floating regfile writes +system.cpu.misc_regfile_reads 49193821 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 775188755 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 88572 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 88572 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129187 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107050 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107050 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65806 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454775 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 520581 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2089088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18665280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20754368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20754368 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 33408 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 291762996 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 770392865 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 86565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 86563 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 321 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 321 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107049 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61854 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 516494 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18659456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20623232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20623232 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 31040 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 290637496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 50495227 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 47495730 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 260303004 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 260347495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 30799 # number of replacements -system.cpu.icache.tags.tagsinuse 1804.677341 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11655246 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 32836 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 354.953283 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 28815 # number of replacements +system.cpu.icache.tags.tagsinuse 1808.840382 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11662045 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 30854 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 377.975141 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1804.677341 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.881190 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.881190 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11655255 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11655255 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11655255 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11655255 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11655255 # number of overall hits -system.cpu.icache.overall_hits::total 11655255 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 36945 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 36945 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 36945 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 36945 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 36945 # number of overall misses -system.cpu.icache.overall_misses::total 36945 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 836533724 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 836533724 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 836533724 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 836533724 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 836533724 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 836533724 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11692200 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11692200 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11692200 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11692200 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11692200 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11692200 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003160 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003160 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003160 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003160 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003160 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003160 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22642.677602 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22642.677602 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22642.677602 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22642.677602 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 965 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1808.840382 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.883223 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.883223 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11662047 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11662047 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11662047 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11662047 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11662047 # number of overall hits +system.cpu.icache.overall_hits::total 11662047 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34957 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34957 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34957 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34957 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34957 # number of overall misses +system.cpu.icache.overall_misses::total 34957 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 813284976 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 813284976 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 813284976 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 813284976 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 813284976 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 813284976 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11697004 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11697004 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11697004 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11697004 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11697004 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11697004 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002989 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002989 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002989 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002989 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002989 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002989 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23265.296679 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23265.296679 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23265.296679 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23265.296679 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23265.296679 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23265.296679 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2987 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 129.869565 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3781 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3781 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3781 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3781 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3781 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3781 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33164 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 33164 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 33164 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 33164 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 33164 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 33164 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 680570772 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 680570772 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 680570772 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 680570772 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 680570772 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 680570772 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002836 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for demand accesses 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overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9142554749 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394365 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.301124 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.946429 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.946429 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955217 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955217 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763933 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.660021 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763933 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.660021 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65845.539352 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73436.661892 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72101.616090 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10029.298742 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10029.298742 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70713.234431 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70713.234431 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 83947 # number of writebacks +system.cpu.l2cache.writebacks::total 83947 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4674 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21857 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26531 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4674 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124114 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128788 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4674 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124114 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128788 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 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MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 308414000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8833465000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9141879000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308213 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.959502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.959502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955235 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955235 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764042 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.666850 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764042 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.666850 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65985.023534 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72924.863888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71702.263390 # average ReadReq mshr miss latency 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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70983.934839 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.865935 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44347537 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 162458 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 272.978474 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 158347 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.859504 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44362534 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 162443 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 273.096003 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.865935 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993375 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993375 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26048299 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26048299 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266707 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15986 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15986 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.859504 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993374 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993374 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26063246 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26063246 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18266759 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18266759 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15989 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15989 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44315006 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44315006 # number of demand (read+write) hits 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-system.cpu.dcache.ReadReq_accesses::cpu.data 26173333 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26173333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44330005 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44330005 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44330005 # number of overall hits +system.cpu.dcache.overall_hits::total 44330005 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124539 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124539 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583142 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583142 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses 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miss cycles +system.cpu.dcache.demand_miss_latency::total 132215195206 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 132215195206 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 132215195206 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26187785 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26187785 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16027 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16027 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16032 # number of LoadLockedReq accesses(hits+misses) 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0.079758 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002558 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002558 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037117 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037117 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037117 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037117 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41921.790969 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41921.790969 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80099.070606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80099.070606 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22310.975610 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 22310.975610 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77304.679001 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77304.679001 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4730 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.028777 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 87.428571 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46037686 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46037686 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46037686 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46037686 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004756 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004756 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079756 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079756 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002682 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002682 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037093 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037093 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037093 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037093 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41885.262568 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41885.262568 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80219.491676 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80219.491676 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 24104.651163 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 24104.651163 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77423.825179 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77423.825179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77423.825179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77423.825179 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3791 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1217 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 149 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.442953 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 93.615385 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129187 # number of writebacks -system.cpu.dcache.writebacks::total 129187 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69592 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69592 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475842 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475842 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545434 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545434 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545434 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545434 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55442 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55442 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107352 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107352 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162794 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162794 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162794 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162794 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2274282063 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2274282063 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8672803924 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8672803924 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947085987 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10947085987 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947085987 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10947085987 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003537 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003537 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41020.923902 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41020.923902 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80788.470862 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80788.470862 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 129111 # number of writebacks +system.cpu.dcache.writebacks::total 129111 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69110 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69110 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475806 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475806 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544916 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544916 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544916 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544916 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55429 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55429 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107336 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107336 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162765 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162765 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162765 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162765 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2263965562 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2263965562 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8681187684 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8681187684 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945153246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10945153246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945153246 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10945153246 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40844.423713 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40844.423713 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80878.621190 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80878.621190 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67245.127921 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67245.127921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67245.127921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67245.127921 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- -- cgit v1.2.3