From fa1fbcf020ee9aacdd4a7a09e81a633e09bad97a Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Mon, 1 Sep 2014 16:55:52 -0500
Subject: stats: updates due to recent ruby and x86 changes Also updates many
 out of date config files.

---
 .../60.bzip2/ref/arm/linux/simple-atomic/config.ini   | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

(limited to 'tests/long/se/60.bzip2/ref/arm/linux/simple-atomic')

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index ad0230a84..ec3a0574d 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -10,13 +10,14 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
 init_param=0
 kernel=
+kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=atomic
@@ -37,12 +38,15 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
 type=AtomicSimpleCPU
 children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
+branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
@@ -72,6 +76,7 @@ simpoint_profile_file=simpoint.bb.gz
 simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
+socket_id=0
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -208,7 +213,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -222,9 +227,19 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
-- 
cgit v1.2.3