From c49e739352b6d6bd665c78c560602d0cff1e6a1a Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 5 Jun 2012 01:23:16 -0400 Subject: all: Update stats for memory per master and total fix. --- .../60.bzip2/ref/x86/linux/simple-timing/stats.txt | 87 ++++++++++++++++++---- 1 file changed, 72 insertions(+), 15 deletions(-) (limited to 'tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt') diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 2bc91e6e3..e2cb03bbf 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 5.923548 # Nu sim_ticks 5923548078000 # Number of ticks simulated final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 747861 # Simulator instruction rate (inst/s) -host_op_rate 1165236 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1472697488 # Simulator tick rate (ticks/s) -host_mem_usage 248420 # Number of bytes of host memory used -host_seconds 4022.24 # Real time elapsed on the host +host_inst_rate 633731 # Simulator instruction rate (inst/s) +host_op_rate 987410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1247949692 # Simulator tick rate (ticks/s) +host_mem_usage 225520 # Number of bytes of host memory used +host_seconds 4746.62 # Real time elapsed on the host sim_insts 3008081057 # Number of instructions simulated sim_ops 4686862651 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 173910080 # Number of bytes read from this memory -system.physmem.bytes_inst_read 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written 75176384 # Number of bytes written to this memory -system.physmem.num_reads 2717345 # Number of read requests responded to by this memory -system.physmem.num_writes 1174631 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 29359107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 12691107 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 42050214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 173866880 # Number of bytes read from this memory +system.physmem.bytes_read::total 173910080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75176384 # Number of bytes written to this memory +system.physmem.bytes_written::total 75176384 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2716670 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2717345 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1174631 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1174631 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 29351814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29359107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12691107 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12691107 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12691107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 29351814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42050214 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 11847096156 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 4013232927 # nu system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 35775000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35775000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 35775000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use @@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 1677713086 # nu system.cpu.dcache.overall_accesses::cpu.data 1677713086 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1677713086 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24617.504171 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24617.504171 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33796.256483 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33796.256483 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26521.034159 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26521.034159 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 214339587000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214339587000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 214339587000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21617.504171 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21617.504171 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30796.256483 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30796.256483 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23521.034159 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23521.034159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23521.034159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2706631 # number of replacements system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use @@ -254,18 +295,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 9112677 system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.252798 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.252868 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471339 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.471339 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.298120 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.298172 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.298120 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.298172 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,18 +349,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108666800000 system.cpu.l2cache.overall_mshr_miss_latency::total 108693800000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.252798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.252868 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471339 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471339 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.298172 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.298172 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- -- cgit v1.2.3