From 0cf36d94095aedef3c51447243c5a3cc14dd5d56 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 22 Apr 2015 20:22:29 -0700 Subject: stats: update for previous changeset Very small differences in IQ-specific O3 stats. --- .../60.bzip2/ref/alpha/tru64/o3-timing/config.ini | 20 +++++++++----- .../se/60.bzip2/ref/alpha/tru64/o3-timing/simerr | 1 + .../se/60.bzip2/ref/alpha/tru64/o3-timing/simout | 7 ++--- .../60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 16 +++++------ .../se/60.bzip2/ref/arm/linux/o3-timing/config.ini | 31 ++++++++++++---------- .../se/60.bzip2/ref/arm/linux/o3-timing/simerr | 1 + .../se/60.bzip2/ref/arm/linux/o3-timing/simout | 9 ++++--- .../se/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 14 +++++----- 8 files changed, 56 insertions(+), 43 deletions(-) (limited to 'tests/long/se/60.bzip2/ref') diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index deabb9ce1..0aec3b5e9 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -133,7 +134,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -147,7 +148,6 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu.dcache] type=BaseCache @@ -587,8 +587,11 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 @@ -609,7 +612,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin kvmInSE=false @@ -642,11 +645,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -677,7 +683,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr index de77515a1..f0a9a7c93 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr @@ -1,3 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index c56412480..488ad0a2f 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2014 12:27:06 -gem5 started Jul 19 2014 12:27:27 +gem5 compiled Apr 22 2015 07:55:25 +gem5 started Apr 22 2015 08:36:02 gem5 executing on phenom command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 679349778000 because target called exit() +Exiting @ tick 672881519500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 0d7c52b8c..58eeef87c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.672882 # Nu sim_ticks 672881519500 # Number of ticks simulated final_tick 672881519500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171066 # Simulator instruction rate (inst/s) -host_op_rate 171066 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66304234 # Simulator tick rate (ticks/s) -host_mem_usage 296744 # Number of bytes of host memory used -host_seconds 10148.39 # Real time elapsed on the host +host_inst_rate 165835 # Simulator instruction rate (inst/s) +host_op_rate 165835 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64276745 # Simulator tick rate (ticks/s) +host_mem_usage 226308 # Number of bytes of host memory used +host_seconds 10468.51 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -413,7 +413,7 @@ system.cpu.iq.iqInstsAdded 2890368727 # Nu system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 2624396643 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 1584497 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1140831193 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 1154325126 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 506084435 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 1345692377 # Number of insts issued each cycle @@ -506,10 +506,10 @@ system.cpu.iq.rate 1.950118 # In system.cpu.iq.fu_busy_cnt 36787651 # FU busy when requested system.cpu.iq.fu_busy_rate 0.014018 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 6630876089 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4030049566 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_writes 4043543263 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 2522176401 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 1981722 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1296863 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 1297099 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 893189 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 2660200136 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 984158 # Number of floating point alu accesses diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 67aea2f65..eadc51bd2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -135,7 +136,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.branchPred] -type=BranchPredictor +type=BiModeBP BTBEntries=2048 BTBTagSize=18 RASSize=16 @@ -145,11 +146,7 @@ eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 numThreads=1 -predType=bi-mode [system.cpu.dcache] type=BaseCache @@ -192,6 +189,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -209,7 +207,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -501,7 +498,7 @@ assoc=2 clk_domain=system.cpu_clk_domain demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true +forward_snoops=false hit_latency=1 is_top_level=true max_miss_count=0 @@ -568,6 +565,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -585,7 +583,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -669,13 +666,16 @@ size=1048576 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -691,7 +691,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin kvmInSE=false @@ -724,11 +724,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -759,7 +762,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr index 5d8946ede..be90b0340 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr @@ -1,2 +1,3 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 288998877..c0864581d 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,12 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 21 2014 11:22:42 -gem5 started Jun 21 2014 21:45:58 +gem5 compiled Apr 22 2015 10:58:25 +gem5 started Apr 22 2015 12:38:48 gem5 executing on phenom command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x5287000 + 0: system.cpu.isa: ISA system set to: 0 0x39c9fd0 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data @@ -25,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 523063504500 because target called exit() +Exiting @ tick 771782683000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index da2c7807d..b2838e173 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.771783 # Nu sim_ticks 771782683000 # Number of ticks simulated final_tick 771782683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141348 # Simulator instruction rate (inst/s) -host_op_rate 152281 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70628369 # Simulator tick rate (ticks/s) -host_mem_usage 310548 # Number of bytes of host memory used -host_seconds 10927.38 # Real time elapsed on the host +host_inst_rate 140791 # Simulator instruction rate (inst/s) +host_op_rate 151681 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70349895 # Simulator tick rate (ticks/s) +host_mem_usage 240068 # Number of bytes of host memory used +host_seconds 10970.63 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1664032415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -495,7 +495,7 @@ system.cpu.iq.iqInstsAdded 1947883742 # Nu system.cpu.iq.iqNonSpecInstsAdded 210 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 1857409514 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 13500100 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 279518916 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 283851537 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 646881302 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 1543486763 # Number of insts issued each cycle @@ -588,7 +588,7 @@ system.cpu.iq.rate 1.203324 # In system.cpu.iq.fu_busy_cnt 405102720 # FU busy when requested system.cpu.iq.fu_busy_rate 0.218101 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 5676908390 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2227415601 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_writes 2231748222 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1805707256 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 208 # Number of floating instruction queue writes -- cgit v1.2.3