From 1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 2 Nov 2012 11:50:06 -0500 Subject: update stats for preceeding changes --- .../ref/alpha/tru64/inorder-timing/config.ini | 68 ++++++++++++++-------- 1 file changed, 45 insertions(+), 23 deletions(-) (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini') diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index db2911eab..402c5cbcd 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] -- cgit v1.2.3