From 6ed567d6002df081dd6cf2db6685d3e66c11272b Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 17 Nov 2016 04:54:14 -0500 Subject: alpha: Remove ALPHA tru64 support and associated tests No one appears to be using it, and it is causing build issues and increases the development and maintenance effort. --- .../ref/alpha/tru64/minor-timing/config.ini | 877 --------------------- .../70.twolf/ref/alpha/tru64/minor-timing/simerr | 7 - .../70.twolf/ref/alpha/tru64/minor-timing/simout | 29 - .../ref/alpha/tru64/minor-timing/stats.txt | 795 ------------------- 4 files changed, 1708 deletions(-) delete mode 100644 tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini delete mode 100755 tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr delete mode 100755 tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout delete mode 100644 tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt (limited to 'tests/long/se/70.twolf/ref/alpha/tru64/minor-timing') diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini deleted file mode 100644 index 35828777f..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini +++ /dev/null @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=twolf smred -cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr deleted file mode 100755 index e0bca4e4e..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout deleted file mode 100755 index 4b089cf00..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout +++ /dev/null @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:43 -gem5 executing on e108600-lin, pid 28042 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/minor-timing - -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 53437621500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt deleted file mode 100644 index 40657583a..000000000 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ /dev/null @@ -1,795 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.053438 # Number of seconds simulated -sim_ticks 53437621500 # Number of ticks simulated -final_tick 53437621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 468238 # Simulator instruction rate (inst/s) -host_op_rate 468238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 272260061 # Simulator tick rate (ticks/s) -host_mem_usage 257916 # Number of bytes of host memory used -host_seconds 196.27 # Real time elapsed on the host -sim_insts 91903089 # Number of instructions simulated -sim_ops 91903089 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory -system.physmem.bytes_read::total 340608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202880 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3796576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2577360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6373936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3796576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3796576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3796576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2577360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6373936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5322 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 340608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 340608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 468 # Per bank write bursts -system.physmem.perBankRdBursts::1 295 # Per bank write bursts -system.physmem.perBankRdBursts::2 308 # Per bank write bursts -system.physmem.perBankRdBursts::3 524 # Per bank write bursts -system.physmem.perBankRdBursts::4 224 # Per bank write bursts -system.physmem.perBankRdBursts::5 238 # Per bank write bursts -system.physmem.perBankRdBursts::6 222 # Per bank write bursts -system.physmem.perBankRdBursts::7 289 # Per bank write bursts -system.physmem.perBankRdBursts::8 254 # Per bank write bursts -system.physmem.perBankRdBursts::9 282 # Per bank write bursts -system.physmem.perBankRdBursts::10 254 # Per bank write bursts -system.physmem.perBankRdBursts::11 261 # Per bank write bursts -system.physmem.perBankRdBursts::12 410 # Per bank write bursts -system.physmem.perBankRdBursts::13 344 # Per bank write bursts -system.physmem.perBankRdBursts::14 501 # Per bank write bursts -system.physmem.perBankRdBursts::15 448 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 53437285500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5322 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4860 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 449 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 981 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 347.009174 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 213.710292 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.985210 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 311 31.70% 31.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 198 20.18% 51.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 103 10.50% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 115 11.72% 74.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 57 5.81% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 30 3.06% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 30 3.06% 86.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 2.65% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 111 11.31% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 981 # Bytes accessed per row activation -system.physmem.totQLat 132267250 # Total ticks spent queuing -system.physmem.totMemAccLat 232054750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24852.92 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43602.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4338 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10040827.79 # Average gap between requests -system.physmem.pageHitRate 81.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3348660 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1772265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18335520 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 173328480.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64638000 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9138240 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 468346770 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 218747040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12435217200 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13392872175 # Total energy per rank (pJ) -system.physmem_0.averagePower 250.626273 # Core power per rank (mW) -system.physmem_0.totalIdleTime 53271099000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 16953500 # Time in different power states -system.physmem_0.memoryStateTime::REF 73680000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51675337000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 569631000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 74922500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1027097500 # Time in different power states -system.physmem_1.actEnergy 3677100 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1950630 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19663560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 191767680.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68393160 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 9924480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 510653310 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 251520000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12393371550 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 13451137230 # Total energy per rank (pJ) -system.physmem_1.averagePower 251.716611 # Core power per rank (mW) -system.physmem_1.totalIdleTime 53261175500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 18732000 # Time in different power states -system.physmem_1.memoryStateTime::REF 81534000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 51486455000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 654968250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 76126500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1119805750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 11450652 # Number of BP lookups -system.cpu.branchPred.condPredicted 8210942 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 765019 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6085116 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5320742 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.438629 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176677 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2073 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 983 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20415218 # DTB read hits -system.cpu.dtb.read_misses 43383 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20458601 # DTB read accesses -system.cpu.dtb.write_hits 6579912 # DTB write hits -system.cpu.dtb.write_misses 276 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6580188 # DTB write accesses -system.cpu.dtb.data_hits 26995130 # DTB hits -system.cpu.dtb.data_misses 43659 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27038789 # DTB accesses -system.cpu.itb.fetch_hits 22968644 # ITB hits -system.cpu.itb.fetch_misses 90 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22968734 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 106875243 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 91903089 # Number of instructions committed -system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2191333 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.162912 # CPI: cycles per instruction -system.cpu.ipc 0.859910 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction -system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction -system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction -system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::MemRead 19433628 21.15% 92.31% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6424338 6.99% 99.30% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 562580 0.61% 99.92% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 76788 0.08% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 91903089 # Class of committed instruction -system.cpu.tickCycles 103792204 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3083039 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.203649 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26572187 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11910.437920 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.203649 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353321 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353321 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53153435 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53153435 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20074003 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20074003 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498184 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498184 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26572187 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26572187 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26572187 # number of overall hits -system.cpu.dcache.overall_hits::total 26572187 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2919 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2919 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3415 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3415 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3415 # number of overall misses -system.cpu.dcache.overall_misses::total 3415 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58822000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58822000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 274731500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 274731500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 333553500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 333553500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 333553500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 333553500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20074499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20074499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26575602 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26575602 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26575602 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26575602 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000449 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000449 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 118592.741935 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 118592.741935 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94118.362453 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 94118.362453 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 97673.060029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 97673.060029 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1176 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1176 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1184 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1184 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1184 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1184 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1743 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2231 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 57888500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 57888500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 165966000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 165966000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 223854500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 223854500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 223854500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 223854500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 118623.975410 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 118623.975410 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95218.588640 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95218.588640 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 13865 # number of replacements -system.cpu.icache.tags.tagsinuse 1642.239495 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22952813 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15830 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1449.956601 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1642.239495 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801875 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801875 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 670 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45953118 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45953118 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22952813 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22952813 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22952813 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22952813 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22952813 # number of overall hits -system.cpu.icache.overall_hits::total 22952813 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15831 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15831 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15831 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15831 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15831 # number of overall misses -system.cpu.icache.overall_misses::total 15831 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 456439000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 456439000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 456439000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 456439000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 456439000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 456439000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22968644 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22968644 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22968644 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22968644 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22968644 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22968644 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28831.975238 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28831.975238 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28831.975238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28831.975238 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 13865 # number of writebacks -system.cpu.icache.writebacks::total 13865 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15831 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15831 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15831 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15831 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15831 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 440609000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 440609000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 440609000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 440609000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 440609000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 440609000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27832.038406 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27832.038406 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3574.446973 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 26761 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5322 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.028373 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.836656 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.610316 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064143 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.044941 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.109083 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5322 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 569 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3605 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.162415 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 261986 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 261986 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 13865 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 13865 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12660 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 12660 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12660 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 12739 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12660 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 12739 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1717 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1717 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3170 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3170 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 435 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 435 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3170 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2152 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5322 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2152 # number of overall misses -system.cpu.l2cache.overall_misses::total 5322 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163078000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 163078000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 283932500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 283932500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 56594000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 56594000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 283932500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 219672000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 503604500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 283932500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 219672000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 503604500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 13865 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 13865 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1743 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1743 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15830 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 15830 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 488 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 488 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15830 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2231 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 18061 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15830 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2231 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 18061 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985083 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.985083 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.200253 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.200253 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.891393 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.891393 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200253 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964590 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.294668 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200253 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964590 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.294668 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94978.450786 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94978.450786 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89568.611987 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89568.611987 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 130101.149425 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 130101.149425 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94626.925968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94626.925968 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1717 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1717 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3170 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3170 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 435 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 435 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3170 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2152 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5322 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2152 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5322 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 145908000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 145908000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252232500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252232500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 52244000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 52244000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252232500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 198152000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 450384500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252232500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 198152000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 450384500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985083 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985083 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.891393 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.891393 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.294668 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.294668 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84978.450786 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84978.450786 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79568.611987 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79568.611987 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 120101.149425 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 120101.149425 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1743 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1743 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 488 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45525 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4619 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50144 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1900480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2050112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 18061 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 18061 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18061 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 30013500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23745000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3346500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5322 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3605 # Transaction distribution -system.membus.trans_dist::ReadExReq 1717 # Transaction distribution -system.membus.trans_dist::ReadExResp 1717 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3605 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10644 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10644 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 340608 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5322 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5322 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5322 # Request fanout histogram -system.membus.reqLayer0.occupancy 6424500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28175000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- -- cgit v1.2.3