From f3585c841e964c98911784a187fc4f081a02a0a6 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 24 Jan 2014 15:29:33 -0600 Subject: stats: update stats for cache occupancy and clock domain changes --- .../ref/sparc/linux/simple-atomic/config.ini | 17 ++++++++- .../70.twolf/ref/sparc/linux/simple-atomic/simerr | 2 -- .../70.twolf/ref/sparc/linux/simple-atomic/simout | 8 ++--- .../ref/sparc/linux/simple-atomic/stats.txt | 13 ++++--- .../ref/sparc/linux/simple-timing/config.ini | 30 +++++++++++++++- .../70.twolf/ref/sparc/linux/simple-timing/simerr | 1 - .../70.twolf/ref/sparc/linux/simple-timing/simout | 8 ++--- .../ref/sparc/linux/simple-timing/stats.txt | 40 +++++++++++++++++++--- 8 files changed, 94 insertions(+), 25 deletions(-) (limited to 'tests/long/se/70.twolf/ref/sparc') diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 450711784..ead3fce75 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +107,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf +eventq_index=0 +executable=/dist/cpu2000/binaries/sparc/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -111,11 +122,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +141,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +151,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr index 7edd901b2..1a4f96712 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr @@ -1,3 +1 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout index 1f1c88e44..522507bd6 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/simout -Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:10:38 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 19:48:57 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 806cadbfa..b414e1534 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.096723 # Nu sim_ticks 96722945000 # Number of ticks simulated final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3763101 # Simulator instruction rate (inst/s) -host_op_rate 3763105 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1881563141 # Simulator tick rate (ticks/s) -host_mem_usage 229516 # Number of bytes of host memory used -host_seconds 51.41 # Real time elapsed on the host +host_inst_rate 2588672 # Simulator instruction rate (inst/s) +host_op_rate 2588674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1294344494 # Simulator tick rate (ticks/s) +host_mem_usage 233760 # Number of bytes of host memory used +host_seconds 74.73 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory @@ -38,6 +40,7 @@ system.physmem.bw_total::total 11055401229 # To system.membus.throughput 11057254439 # Throughput (bytes/s) system.membus.data_through_bus 1069490213 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 193445891 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index bac902cb5..5f60b5786 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -147,6 +164,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +173,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +188,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +206,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +216,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf +eventq_index=0 +executable=/dist/cpu2000/binaries/sparc/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -207,11 +231,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +250,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +260,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout index 139366506..cbae3bd7a 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:08:55 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 19:50:23 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 471075dde..4c0f0b47e 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.270563 # Nu sim_ticks 270563082000 # Number of ticks simulated final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 872463 # Simulator instruction rate (inst/s) -host_op_rate 872464 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1220278409 # Simulator tick rate (ticks/s) -host_mem_usage 236504 # Number of bytes of host memory used -host_seconds 221.72 # Real time elapsed on the host +host_inst_rate 1313314 # Simulator instruction rate (inst/s) +host_op_rate 1313315 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1836878526 # Simulator tick rate (ticks/s) +host_mem_usage 242660 # Number of bytes of host memory used +host_seconds 147.30 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory system.physmem.bytes_read::total 331072 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 5173000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 541126164 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -74,6 +77,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses +system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits @@ -156,6 +168,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 116103 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 116103 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits @@ -283,6 +304,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits -- cgit v1.2.3