From b63631536d974f31cf99ee280271dc0f7b4c746f Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 19 Aug 2013 03:52:36 -0400 Subject: stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size. --- .../se/70.twolf/ref/x86/linux/o3-timing/stats.txt | 87 +++++++++++----------- 1 file changed, 43 insertions(+), 44 deletions(-) (limited to 'tests/long/se/70.twolf/ref/x86/linux/o3-timing') diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 2e8d78059..53040adf9 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.144471 # Nu sim_ticks 144470654000 # Number of ticks simulated final_tick 144470654000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76550 # Simulator instruction rate (inst/s) -host_op_rate 128304 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83736451 # Simulator tick rate (ticks/s) -host_mem_usage 279024 # Number of bytes of host memory used -host_seconds 1725.30 # Real time elapsed on the host +host_inst_rate 75912 # Simulator instruction rate (inst/s) +host_op_rate 127236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83039301 # Simulator tick rate (ticks/s) +host_mem_usage 277792 # Number of bytes of host memory used +host_seconds 1739.79 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362962 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1500429 # In system.physmem.bw_total::cpu.inst 1500429 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 865172 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2365602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5340 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5492 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 5340 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 5340 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 341760 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 341760 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 152 # Reqs where no action is needed system.physmem.perBankRdReqs::0 286 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 358 # Track reads on a per bank basis @@ -242,11 +243,9 @@ system.membus.trans_dist::ReadExReq 1530 # Tr system.membus.trans_dist::ReadExResp 1530 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10983 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10983 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 10983 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 10983 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 341696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 341696 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 341696 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -531,12 +530,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 153 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 153 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13393 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4315 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 17708 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 423616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 552320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13393 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17708 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 552320 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 552320 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 9856 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 4483500 # Layer occupancy (ticks) @@ -545,15 +544,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 10832250 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3515652 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 4654 # number of replacements -system.cpu.icache.tags.tagsinuse 1616.215170 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22351029 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6622 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3375.268650 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1616.215170 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.789168 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.789168 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 4654 # number of replacements +system.cpu.icache.tags.tagsinuse 1616.215170 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22351029 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6622 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3375.268650 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1616.215170 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.789168 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.789168 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 22351029 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 22351029 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 22351029 # number of demand (read+write) hits @@ -629,19 +628,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 38650.612637 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38650.612637 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 38650.612637 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2537.222896 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3276 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3813 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.859166 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2537.222896 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3276 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3813 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.859166 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 1.748933 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2223.089774 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 312.384188 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2223.089774 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 312.384188 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.067843 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.009533 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.077430 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.077430 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3232 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 38 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3270 # number of ReadReq hits @@ -781,15 +780,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53112.234357 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52681.515617 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52954.736941 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 56 # number of replacements -system.cpu.dcache.tags.tagsinuse 1433.333580 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66124025 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33111.680020 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1433.333580 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.349935 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.349935 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 56 # number of replacements +system.cpu.dcache.tags.tagsinuse 1433.333580 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66124025 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33111.680020 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1433.333580 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.349935 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.349935 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 45609763 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 45609763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514039 # number of WriteReq hits -- cgit v1.2.3