From 1d933447fc62de67db938970a8308ac47189fd96 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Thu, 2 Jun 2016 14:14:36 +0100 Subject: stats: Update to match ARM ISA changes --- .../long/se/70.twolf/ref/arm/linux/o3-timing/config.ini | 9 +++++++++ tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr | 1 + tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout | 4 +--- tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | 16 ++++++++-------- 4 files changed, 19 insertions(+), 11 deletions(-) (limited to 'tests/long/se/70.twolf') diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 3195ac533..71957ae5a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -147,8 +149,15 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr index f9e2ef3b2..341b479f7 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr @@ -1 +1,2 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index e145846b2..00456d1c3 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -8,8 +8,6 @@ gem5 started Mar 15 2016 20:14:36 gem5 executing on dinar2c11, pid 10702 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 85490431000 because target called exit() +122 123 124 Exiting @ tick 84937723500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 5e6d9ee12..a41b2e194 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.084938 # Nu sim_ticks 84937723500 # Number of ticks simulated final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96546 # Simulator instruction rate (inst/s) -host_op_rate 101775 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47592642 # Simulator tick rate (ticks/s) -host_mem_usage 268276 # Number of bytes of host memory used -host_seconds 1784.68 # Real time elapsed on the host +host_inst_rate 205804 # Simulator instruction rate (inst/s) +host_op_rate 216952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 101452217 # Simulator tick rate (ticks/s) +host_mem_usage 314712 # Number of bytes of host memory used +host_seconds 837.22 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -436,7 +436,7 @@ system.cpu.rename.LQFullEvents 2280960 # Nu system.cpu.rename.SQFullEvents 36243 # Number of times rename has blocked due to SQ full system.cpu.rename.FullRegisterEvents 27083 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 481449871 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1191735135 # Number of register rename lookups that rename has made +system.cpu.rename.RenameLookups 1187780717 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 296461789 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3004325 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed @@ -453,7 +453,7 @@ system.cpu.iq.iqNonSpecInstsAdded 45955 # Nu system.cpu.iq.iqInstsIssued 214411803 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 5187874 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 82208585 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 217092419 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 216955908 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 169120520 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.267805 # Number of insts issued each cycle @@ -674,7 +674,7 @@ system.cpu.fp_regfile_reads 2904222 # nu system.cpu.fp_regfile_writes 2441435 # number of floating regfile writes system.cpu.cc_regfile_reads 708194084 # number of cc regfile reads system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes -system.cpu.misc_regfile_reads 59249203 # number of misc regfile reads +system.cpu.misc_regfile_reads 57440840 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes system.cpu.dcache.tags.replacements 72581 # number of replacements system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use -- cgit v1.2.3