From f3585c841e964c98911784a187fc4f081a02a0a6 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Fri, 24 Jan 2014 15:29:33 -0600
Subject: stats: update stats for cache occupancy and clock domain changes

---
 .../se/10.mcf/ref/arm/linux/o3-timing/config.ini   |   10 +-
 .../long/se/10.mcf/ref/arm/linux/o3-timing/simerr  |    1 -
 .../long/se/10.mcf/ref/arm/linux/o3-timing/simout  |    8 +-
 .../se/10.mcf/ref/arm/linux/o3-timing/stats.txt    |   37 +-
 .../10.mcf/ref/arm/linux/simple-atomic/config.ini  |   21 +-
 .../se/10.mcf/ref/arm/linux/simple-atomic/simerr   |    1 -
 .../se/10.mcf/ref/arm/linux/simple-atomic/simout   |    8 +-
 .../10.mcf/ref/arm/linux/simple-atomic/stats.txt   |   13 +-
 .../10.mcf/ref/arm/linux/simple-timing/config.ini  |   34 +-
 .../se/10.mcf/ref/arm/linux/simple-timing/simerr   |    1 -
 .../se/10.mcf/ref/arm/linux/simple-timing/simout   |    8 +-
 .../10.mcf/ref/arm/linux/simple-timing/stats.txt   |   38 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |   19 +-
 .../se/10.mcf/ref/sparc/linux/simple-atomic/simerr |    2 -
 .../se/10.mcf/ref/sparc/linux/simple-atomic/simout |    8 +-
 .../10.mcf/ref/sparc/linux/simple-atomic/stats.txt |   13 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   32 +-
 .../se/10.mcf/ref/sparc/linux/simple-timing/simerr |    1 -
 .../se/10.mcf/ref/sparc/linux/simple-timing/simout |    8 +-
 .../10.mcf/ref/sparc/linux/simple-timing/stats.txt |   38 +-
 .../se/10.mcf/ref/x86/linux/o3-timing/config.ini   |   10 +-
 .../long/se/10.mcf/ref/x86/linux/o3-timing/simerr  |    1 -
 .../long/se/10.mcf/ref/x86/linux/o3-timing/simout  |   10 +-
 .../se/10.mcf/ref/x86/linux/o3-timing/stats.txt    |   38 +-
 .../10.mcf/ref/x86/linux/simple-atomic/config.ini  |   22 +-
 .../se/10.mcf/ref/x86/linux/simple-atomic/simerr   |    1 -
 .../se/10.mcf/ref/x86/linux/simple-atomic/simout   |    6 +-
 .../10.mcf/ref/x86/linux/simple-atomic/stats.txt   |   14 +-
 .../10.mcf/ref/x86/linux/simple-timing/config.ini  |   35 +-
 .../se/10.mcf/ref/x86/linux/simple-timing/simerr   |    1 -
 .../se/10.mcf/ref/x86/linux/simple-timing/simout   |    6 +-
 .../10.mcf/ref/x86/linux/simple-timing/stats.txt   |   38 +-
 .../20.parser/ref/arm/linux/o3-timing/config.ini   |   10 +-
 .../se/20.parser/ref/arm/linux/o3-timing/simerr    |    1 -
 .../se/20.parser/ref/arm/linux/o3-timing/simout    |    8 +-
 .../se/20.parser/ref/arm/linux/o3-timing/stats.txt |   39 +-
 .../ref/arm/linux/simple-atomic/config.ini         |   21 +-
 .../20.parser/ref/arm/linux/simple-atomic/simerr   |    1 -
 .../20.parser/ref/arm/linux/simple-atomic/simout   |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt          |   13 +-
 .../ref/arm/linux/simple-timing/config.ini         |   34 +-
 .../20.parser/ref/arm/linux/simple-timing/simerr   |    1 -
 .../20.parser/ref/arm/linux/simple-timing/simout   |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt          |   39 +-
 .../20.parser/ref/x86/linux/o3-timing/config.ini   |   10 +-
 .../se/20.parser/ref/x86/linux/o3-timing/simerr    |    1 -
 .../se/20.parser/ref/x86/linux/o3-timing/simout    |   35 +-
 .../se/20.parser/ref/x86/linux/o3-timing/stats.txt | 1598 ++++++++++----------
 .../ref/x86/linux/simple-atomic/config.ini         |   22 +-
 .../20.parser/ref/x86/linux/simple-atomic/simerr   |    1 -
 .../20.parser/ref/x86/linux/simple-atomic/simout   |    6 +-
 .../ref/x86/linux/simple-atomic/stats.txt          |   14 +-
 .../ref/x86/linux/simple-timing/config.ini         |   35 +-
 .../20.parser/ref/x86/linux/simple-timing/simerr   |    1 -
 .../20.parser/ref/x86/linux/simple-timing/simout   |    6 +-
 .../ref/x86/linux/simple-timing/stats.txt          |   40 +-
 .../ref/alpha/tru64/inorder-timing/config.ini      |   37 +-
 .../30.eon/ref/alpha/tru64/inorder-timing/simerr   |    1 -
 .../30.eon/ref/alpha/tru64/inorder-timing/simout   |    8 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt       |   39 +-
 .../se/30.eon/ref/alpha/tru64/o3-timing/config.ini |    9 +-
 .../se/30.eon/ref/alpha/tru64/o3-timing/simerr     |    1 -
 .../se/30.eon/ref/alpha/tru64/o3-timing/simout     |    8 +-
 .../se/30.eon/ref/alpha/tru64/o3-timing/stats.txt  |   38 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |   18 +-
 .../se/30.eon/ref/alpha/tru64/simple-atomic/simerr |    2 -
 .../se/30.eon/ref/alpha/tru64/simple-atomic/simout |    6 +-
 .../30.eon/ref/alpha/tru64/simple-atomic/stats.txt |   13 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |   31 +-
 .../se/30.eon/ref/alpha/tru64/simple-timing/simerr |    1 -
 .../se/30.eon/ref/alpha/tru64/simple-timing/simout |    6 +-
 .../30.eon/ref/alpha/tru64/simple-timing/stats.txt |   40 +-
 .../se/30.eon/ref/arm/linux/o3-timing/config.ini   |    8 +-
 .../long/se/30.eon/ref/arm/linux/o3-timing/simerr  |    1 -
 .../long/se/30.eon/ref/arm/linux/o3-timing/simout  |    8 +-
 .../se/30.eon/ref/arm/linux/o3-timing/stats.txt    |   40 +-
 .../30.eon/ref/arm/linux/simple-atomic/config.ini  |   19 +-
 .../se/30.eon/ref/arm/linux/simple-atomic/simerr   |    1 -
 .../se/30.eon/ref/arm/linux/simple-atomic/simout   |    8 +-
 .../30.eon/ref/arm/linux/simple-atomic/stats.txt   |   13 +-
 .../30.eon/ref/arm/linux/simple-timing/config.ini  |   32 +-
 .../se/30.eon/ref/arm/linux/simple-timing/simerr   |    1 -
 .../se/30.eon/ref/arm/linux/simple-timing/simout   |    8 +-
 .../30.eon/ref/arm/linux/simple-timing/stats.txt   |   40 +-
 .../ref/alpha/tru64/o3-timing/config.ini           |    9 +-
 .../se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr |    1 -
 .../se/40.perlbmk/ref/alpha/tru64/o3-timing/simout |   10 +-
 .../40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt |   39 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |   18 +-
 .../ref/alpha/tru64/simple-atomic/simerr           |    2 -
 .../ref/alpha/tru64/simple-atomic/simout           |    6 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |   13 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |   31 +-
 .../ref/alpha/tru64/simple-timing/simerr           |    1 -
 .../ref/alpha/tru64/simple-timing/simout           |    6 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   39 +-
 .../40.perlbmk/ref/arm/linux/o3-timing/config.ini  |    8 +-
 .../se/40.perlbmk/ref/arm/linux/o3-timing/simerr   |    1 -
 .../se/40.perlbmk/ref/arm/linux/o3-timing/simout   |    8 +-
 .../40.perlbmk/ref/arm/linux/o3-timing/stats.txt   |   40 +-
 .../ref/arm/linux/simple-atomic/config.ini         |   19 +-
 .../40.perlbmk/ref/arm/linux/simple-atomic/simerr  |    1 -
 .../40.perlbmk/ref/arm/linux/simple-atomic/simout  |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt          |   13 +-
 .../ref/arm/linux/simple-timing/config.ini         |   32 +-
 .../40.perlbmk/ref/arm/linux/simple-timing/simerr  |    1 -
 .../40.perlbmk/ref/arm/linux/simple-timing/simout  |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt          |   38 +-
 .../ref/alpha/tru64/inorder-timing/config.ini      |    9 +-
 .../ref/alpha/tru64/inorder-timing/simerr          |    1 -
 .../ref/alpha/tru64/inorder-timing/simout          |    8 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt       |   37 +-
 .../50.vortex/ref/alpha/tru64/o3-timing/config.ini |    9 +-
 .../se/50.vortex/ref/alpha/tru64/o3-timing/simerr  |    1 -
 .../se/50.vortex/ref/alpha/tru64/o3-timing/simout  |    8 +-
 .../50.vortex/ref/alpha/tru64/o3-timing/stats.txt  |   38 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |   18 +-
 .../50.vortex/ref/alpha/tru64/simple-atomic/simerr |    2 -
 .../50.vortex/ref/alpha/tru64/simple-atomic/simout |    6 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |   13 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |   31 +-
 .../50.vortex/ref/alpha/tru64/simple-timing/simerr |    1 -
 .../50.vortex/ref/alpha/tru64/simple-timing/simout |    6 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   37 +-
 .../50.vortex/ref/arm/linux/o3-timing/config.ini   |    8 +-
 .../se/50.vortex/ref/arm/linux/o3-timing/simerr    |    1 -
 .../se/50.vortex/ref/arm/linux/o3-timing/simout    |    8 +-
 .../se/50.vortex/ref/arm/linux/o3-timing/stats.txt |   37 +-
 .../ref/arm/linux/simple-atomic/config.ini         |   19 +-
 .../50.vortex/ref/arm/linux/simple-atomic/simerr   |    1 -
 .../50.vortex/ref/arm/linux/simple-atomic/simout   |    8 +-
 .../ref/arm/linux/simple-atomic/stats.txt          |   13 +-
 .../ref/arm/linux/simple-timing/config.ini         |   32 +-
 .../50.vortex/ref/arm/linux/simple-timing/simerr   |    1 -
 .../50.vortex/ref/arm/linux/simple-timing/simout   |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt          |   37 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |   17 +-
 .../50.vortex/ref/sparc/linux/simple-atomic/simerr |    2 -
 .../50.vortex/ref/sparc/linux/simple-atomic/simout |    8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   13 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   30 +-
 .../50.vortex/ref/sparc/linux/simple-timing/simerr |    1 -
 .../50.vortex/ref/sparc/linux/simple-timing/simout |    8 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   38 +-
 .../ref/alpha/tru64/inorder-timing/config.ini      |    9 +-
 .../60.bzip2/ref/alpha/tru64/inorder-timing/simerr |    1 -
 .../60.bzip2/ref/alpha/tru64/inorder-timing/simout |    8 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt       |   36 +-
 .../60.bzip2/ref/alpha/tru64/o3-timing/config.ini  |    9 +-
 .../se/60.bzip2/ref/alpha/tru64/o3-timing/simerr   |    1 -
 .../se/60.bzip2/ref/alpha/tru64/o3-timing/simout   |   10 +-
 .../60.bzip2/ref/alpha/tru64/o3-timing/stats.txt   |   37 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |   18 +-
 .../60.bzip2/ref/alpha/tru64/simple-atomic/simerr  |    2 -
 .../60.bzip2/ref/alpha/tru64/simple-atomic/simout  |    6 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |   13 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |   31 +-
 .../60.bzip2/ref/alpha/tru64/simple-timing/simerr  |    1 -
 .../60.bzip2/ref/alpha/tru64/simple-timing/simout  |    6 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   37 +-
 .../se/60.bzip2/ref/arm/linux/o3-timing/config.ini |    8 +-
 .../se/60.bzip2/ref/arm/linux/o3-timing/simerr     |    1 -
 .../se/60.bzip2/ref/arm/linux/o3-timing/simout     |    8 +-
 .../se/60.bzip2/ref/arm/linux/o3-timing/stats.txt  |   37 +-
 .../ref/arm/linux/simple-atomic/config.ini         |   19 +-
 .../se/60.bzip2/ref/arm/linux/simple-atomic/simerr |    1 -
 .../se/60.bzip2/ref/arm/linux/simple-atomic/simout |    8 +-
 .../60.bzip2/ref/arm/linux/simple-atomic/stats.txt |   13 +-
 .../ref/arm/linux/simple-timing/config.ini         |   32 +-
 .../se/60.bzip2/ref/arm/linux/simple-timing/simerr |    1 -
 .../se/60.bzip2/ref/arm/linux/simple-timing/simout |    8 +-
 .../60.bzip2/ref/arm/linux/simple-timing/stats.txt |   38 +-
 .../ref/x86/linux/simple-atomic/config.ini         |   20 +-
 .../se/60.bzip2/ref/x86/linux/simple-atomic/simerr |    1 -
 .../se/60.bzip2/ref/x86/linux/simple-atomic/simout |    6 +-
 .../60.bzip2/ref/x86/linux/simple-atomic/stats.txt |   14 +-
 .../ref/x86/linux/simple-timing/config.ini         |   33 +-
 .../se/60.bzip2/ref/x86/linux/simple-timing/simerr |    1 -
 .../se/60.bzip2/ref/x86/linux/simple-timing/simout |    6 +-
 .../60.bzip2/ref/x86/linux/simple-timing/stats.txt |   38 +-
 .../ref/alpha/tru64/inorder-timing/config.ini      |    9 +-
 .../70.twolf/ref/alpha/tru64/inorder-timing/simerr |    1 -
 .../70.twolf/ref/alpha/tru64/inorder-timing/simout |   10 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt       |   40 +-
 .../70.twolf/ref/alpha/tru64/o3-timing/config.ini  |    9 +-
 .../se/70.twolf/ref/alpha/tru64/o3-timing/simerr   |    1 -
 .../se/70.twolf/ref/alpha/tru64/o3-timing/simout   |   10 +-
 .../70.twolf/ref/alpha/tru64/o3-timing/stats.txt   |   39 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |   18 +-
 .../70.twolf/ref/alpha/tru64/simple-atomic/simerr  |    2 -
 .../70.twolf/ref/alpha/tru64/simple-atomic/simout  |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |   13 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |   31 +-
 .../70.twolf/ref/alpha/tru64/simple-timing/simerr  |    1 -
 .../70.twolf/ref/alpha/tru64/simple-timing/simout  |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   40 +-
 .../se/70.twolf/ref/arm/linux/o3-timing/config.ini |    8 +-
 .../se/70.twolf/ref/arm/linux/o3-timing/simerr     |    1 -
 .../se/70.twolf/ref/arm/linux/o3-timing/simout     |   10 +-
 .../se/70.twolf/ref/arm/linux/o3-timing/stats.txt  |   40 +-
 .../ref/arm/linux/simple-atomic/config.ini         |   19 +-
 .../se/70.twolf/ref/arm/linux/simple-atomic/simerr |    1 -
 .../se/70.twolf/ref/arm/linux/simple-atomic/simout |    8 +-
 .../70.twolf/ref/arm/linux/simple-atomic/stats.txt |   13 +-
 .../ref/arm/linux/simple-timing/config.ini         |   32 +-
 .../se/70.twolf/ref/arm/linux/simple-timing/simerr |    1 -
 .../se/70.twolf/ref/arm/linux/simple-timing/simout |    8 +-
 .../70.twolf/ref/arm/linux/simple-timing/stats.txt |   40 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |   17 +-
 .../70.twolf/ref/sparc/linux/simple-atomic/simerr  |    2 -
 .../70.twolf/ref/sparc/linux/simple-atomic/simout  |    8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |   13 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   30 +-
 .../70.twolf/ref/sparc/linux/simple-timing/simerr  |    1 -
 .../70.twolf/ref/sparc/linux/simple-timing/simout  |    8 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   40 +-
 .../se/70.twolf/ref/x86/linux/o3-timing/config.ini |    8 +-
 .../se/70.twolf/ref/x86/linux/o3-timing/simerr     |    1 -
 .../se/70.twolf/ref/x86/linux/o3-timing/simout     |   10 +-
 .../se/70.twolf/ref/x86/linux/o3-timing/stats.txt  |   41 +-
 .../ref/x86/linux/simple-atomic/config.ini         |   20 +-
 .../se/70.twolf/ref/x86/linux/simple-atomic/simerr |    1 -
 .../se/70.twolf/ref/x86/linux/simple-atomic/simout |    8 +-
 .../70.twolf/ref/x86/linux/simple-atomic/stats.txt |   14 +-
 .../ref/x86/linux/simple-timing/config.ini         |   33 +-
 .../se/70.twolf/ref/x86/linux/simple-timing/simerr |    1 -
 .../se/70.twolf/ref/x86/linux/simple-timing/simout |    8 +-
 .../70.twolf/ref/x86/linux/simple-timing/stats.txt |   41 +-
 228 files changed, 3533 insertions(+), 1450 deletions(-)

(limited to 'tests/long/se')

diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index ab0c1f304..09e0d3e34 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -159,6 +159,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,9 +632,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/dist/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index f7ab26f15..88b266667 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 01:59:02
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:37:28
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -23,4 +23,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 26877484000 because target called exit()
+Exiting @ tick 26911413000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index a6e3b7d23..f2d38a430 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.026911                       # Nu
 sim_ticks                                 26911413000                       # Number of ticks simulated
 final_tick                                26911413000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 116759                       # Simulator instruction rate (inst/s)
-host_op_rate                                   117598                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               34685583                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 427272                       # Number of bytes of host memory used
-host_seconds                                   775.87                       # Real time elapsed on the host
+host_inst_rate                                 180996                       # Simulator instruction rate (inst/s)
+host_op_rate                                   182296                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               53768206                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 381936                       # Number of bytes of host memory used
+host_seconds                                   500.51                       # Real time elapsed on the host
 sim_insts                                    90589798                       # Number of instructions simulated
 sim_ops                                      91240351                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             45440                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            947712                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               993152                       # Number of bytes read from this memory
@@ -303,6 +305,7 @@ system.membus.reqLayer0.occupancy            19253000                       # La
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.respLayer1.occupancy          145189999                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                26686306                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          22003847                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            843168                       # Number of conditional branches incorrect
@@ -648,6 +651,14 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   632.612747                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.308893                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.308893                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          732                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          676                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.357422                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          27691521                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27691521                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     13844401                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        13844401                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      13844401                       # number of demand (read+write) hits
@@ -736,6 +747,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.301529
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.018879                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.007075                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.327483                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15501                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          513                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1300                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13618                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.473053                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         15189018                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15189018                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           24                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       903618                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         903642                       # number of ReadReq hits
@@ -893,6 +913,13 @@ system.cpu.dcache.tags.warmup_cycle        8006035000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  3671.733270                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.896419                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.896419                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          448                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3128                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          520                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          59988680                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         59988680                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     23603772                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        23603772                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      4532846                       # number of WriteReq hits
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
index e8dafcae9..8155e41d5 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@ icache_port=system.membus.slave[1]
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,9 +141,10 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -143,11 +156,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
index a5dbe98d0..35b926dc8 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:18:17
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:39:34
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 397354d07..be3e03048 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.054241                       # Nu
 sim_ticks                                 54240661000                       # Number of ticks simulated
 final_tick                                54240661000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2267620                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2283902                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1357548360                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 366572                       # Number of bytes of host memory used
-host_seconds                                    39.95                       # Real time elapsed on the host
+host_inst_rate                                2327254                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2343964                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1393249116                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 371180                       # Number of bytes of host memory used
+host_seconds                                    38.93                       # Real time elapsed on the host
 sim_insts                                    90602407                       # Number of instructions simulated
 sim_ops                                      91252960                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         431323080                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          90016598                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            521339678                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@ system.physmem.bw_total::total             9960199711                       # To
 system.membus.throughput                   9960199711                       # Throughput (bytes/s)
 system.membus.data_through_bus              540247816                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index 08fdda12e..f9a7d69b3 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,9 +250,10 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -239,11 +265,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
index c84bc1d04..92da3b737 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:24:43
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:40:24
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index e75e7c0cb..f99edcca6 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.147136                       # Nu
 sim_ticks                                147135976000                       # Number of ticks simulated
 final_tick                               147135976000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 529408                       # Simulator instruction rate (inst/s)
-host_op_rate                                   533204                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              859987474                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 373720                       # Number of bytes of host memory used
-host_seconds                                   171.09                       # Real time elapsed on the host
+host_inst_rate                                1334589                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1344158                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2167949307                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 379884                       # Number of bytes of host memory used
+host_seconds                                    67.87                       # Real time elapsed on the host
 sim_insts                                    90576861                       # Number of instructions simulated
 sim_ops                                      91226312                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             36992                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            944768                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               981760                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy            15340000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy          138060000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -116,6 +119,14 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   510.071144                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.249058                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.249058                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          597                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          552                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.291504                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         215662141                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        215662141                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    107830172                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       107830172                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     107830172                       # number of demand (read+write) hits
@@ -198,6 +209,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.270902
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.015110                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.005897                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.291909                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15323                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           95                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1478                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13704                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.467621                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         15179780                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15179780                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           21                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       899975                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         899996                       # number of ReadReq hits
@@ -330,6 +350,14 @@ system.cpu.dcache.tags.warmup_cycle       54472394000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  3565.217259                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.870414                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.870414                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1322                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2583                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          55531122                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         55531122                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     21649218                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        21649218                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      4688372                       # number of WriteReq hits
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index de11b33de..6f2d20a8e 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,25 @@ icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,9 +107,10 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+eventq_index=0
+executable=/dist/cpu2000/binaries/sparc/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -111,11 +122,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +141,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +151,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
index 7edd901b2..1a4f96712 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
@@ -1,3 +1 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
index db2db18f1..a8897be0c 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:07:55
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:41:52
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index 9196a1276..c49cf6b74 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.122216                       # Nu
 sim_ticks                                122215823500                       # Number of ticks simulated
 final_tick                               122215823500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2226348                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2226440                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1115942635                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 357000                       # Number of bytes of host memory used
-host_seconds                                   109.52                       # Real time elapsed on the host
+host_inst_rate                                3086610                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3086737                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1547143112                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 361240                       # Number of bytes of host memory used
+host_seconds                                    78.99                       # Real time elapsed on the host
 sim_insts                                   243825150                       # Number of instructions simulated
 sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         977685992                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         328674008                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           1306360000                       # Number of bytes read from this memory
@@ -38,6 +40,7 @@ system.physmem.bw_total::total            11438503207                       # To
 system.membus.throughput                  11438757576                       # Throughput (bytes/s)
 system.membus.data_through_bus             1397997177                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
 system.cpu.numCycles                        244431648                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index 882273887..95a36ae61 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -147,6 +164,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +173,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +188,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +206,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,9 +216,10 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+eventq_index=0
+executable=/dist/cpu2000/binaries/sparc/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -207,11 +231,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +250,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +260,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
index 1e103dc44..009ef705f 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:07:47
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:43:22
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 7e2d4c700..a787dee3c 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.361489                       # Nu
 sim_ticks                                361488530000                       # Number of ticks simulated
 final_tick                               361488530000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 810264                       # Simulator instruction rate (inst/s)
-host_op_rate                                   810297                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1201274596                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 365008                       # Number of bytes of host memory used
-host_seconds                                   300.92                       # Real time elapsed on the host
+host_inst_rate                                1454320                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1454380                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2156135283                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 371132                       # Number of bytes of host memory used
+host_seconds                                   167.66                       # Real time elapsed on the host
 sim_insts                                   243825150                       # Number of instructions simulated
 sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             56256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            942336                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               998592                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy            15603000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy          140427000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
 system.cpu.numCycles                        722977060                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -74,6 +77,14 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   725.412977                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.354206                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.354206                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          857                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          781                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.418457                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         488843880                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        488843880                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    244420617                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       244420617                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     244420617                       # number of demand (read+write) hits
@@ -156,6 +167,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.270009
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.022541                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.004404                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.296955                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15586                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1385                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13986                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.475647                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         15068052                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15068052                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       892700                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         892703                       # number of ReadReq hits
@@ -288,6 +308,14 @@ system.cpu.dcache.tags.warmup_cycle      134366265000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  3562.469056                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.869743                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.869743                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1418                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2513                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           46                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         211192111                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        211192111                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     81327576                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        81327576                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     22855241                       # number of WriteReq hits
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index a7b21f16f..0b4c31c18 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -165,6 +165,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -181,6 +182,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -520,6 +522,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -536,6 +539,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,9 +632,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index 0a86dbd97..c033cc0d9 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:42:09
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 19:53:01
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -16,12 +16,12 @@ All Rights Reserved.
 nodes                      : 500
 active arcs                : 1905
 simplex iterations         : 1502
+info: Increasing stack size by one page.
 flow value                 : 4990014995
 new implicit arcs          : 23867
 active arcs                : 25772
 simplex iterations         : 2663
-info: Increasing stack size by one page.
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 65497052500 because target called exit()
+Exiting @ tick 65613727000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 999935db6..167e49074 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.065614                       # Nu
 sim_ticks                                 65613727000                       # Number of ticks simulated
 final_tick                                65613727000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72100                       # Simulator instruction rate (inst/s)
-host_op_rate                                   126957                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               29943715                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 436724                       # Number of bytes of host memory used
-host_seconds                                  2191.24                       # Real time elapsed on the host
+host_inst_rate                                 111661                       # Simulator instruction rate (inst/s)
+host_op_rate                                   196618                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               46373693                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 390932                       # Number of bytes of host memory used
+host_seconds                                  1414.89                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             63616                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           1883136                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              1946752                       # Number of bytes read from this memory
@@ -300,6 +302,7 @@ system.membus.reqLayer0.occupancy            34950500                       # La
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.respLayer1.occupancy          284209000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                33859770                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          33859770                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            774913                       # Number of conditional branches incorrect
@@ -309,6 +312,7 @@ system.cpu.branchPred.BTBCorrect                    0                       # Nu
 system.cpu.branchPred.BTBHitPct             99.461636                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 5016745                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect               5399                       # Number of incorrect RAS predictions.
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
 system.cpu.numCycles                        131227460                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -599,6 +603,14 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   819.642194                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.400216                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.400216                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          954                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          867                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.465820                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          51151797                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         51151797                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     25574088                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        25574088                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      25574088                       # number of demand (read+write) hits
@@ -687,6 +699,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.607028
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020463                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.007473                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.634964                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29922                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          773                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1381                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27646                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.913147                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         33268796                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        33268796                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           17                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1993866                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1993883                       # number of ReadReq hits
@@ -821,6 +842,13 @@ system.cpu.dcache.tags.warmup_cycle       20690834250                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4069.513707                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.993534                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.993534                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          593                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3349                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          154                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         150351466                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        150351466                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     40071930                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        40071930                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     31341693                       # number of WriteReq hits
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
index 433f51b0f..6769a8e07 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -76,16 +81,19 @@ icache_port=system.membus.slave[1]
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
@@ -93,6 +101,7 @@ port=system.membus.slave[4]
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -103,22 +112,26 @@ pio=system.membus.master[1]
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -128,9 +141,10 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -142,11 +156,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -159,6 +175,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -168,5 +185,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
index 98402c27f..ea41249d4 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:43:36
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 20:16:46
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index d28c1e1a8..17feba7fa 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.168950                       # Nu
 sim_ticks                                168950040000                       # Number of ticks simulated
 final_tick                               168950040000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1229454                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2164871                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1314755229                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 378084                       # Number of bytes of host memory used
-host_seconds                                   128.50                       # Real time elapsed on the host
+host_inst_rate                                1603557                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2823605                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1714813271                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 379092                       # Number of bytes of host memory used
+host_seconds                                    98.52                       # Real time elapsed on the host
 sim_insts                                   157988548                       # Number of instructions simulated
 sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        1741569312                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         717246013                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           2458815325                       # Number of bytes read from this memory
@@ -36,6 +38,8 @@ system.physmem.bw_total::total            15992825110                       # To
 system.membus.throughput                  15992825110                       # Throughput (bytes/s)
 system.membus.data_through_bus             2701988442                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
 system.cpu.numCycles                        337900081                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index ffd9b2f5e..9efa1f6d6 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -69,6 +74,7 @@ icache_port=system.cpu.icache.cpu_side
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dcache]
 type=BaseCache
@@ -76,6 +82,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -84,6 +91,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -98,18 +106,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
@@ -120,6 +132,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -128,6 +141,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -142,12 +156,15 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -158,16 +175,19 @@ pio=system.membus.master[1]
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
@@ -178,6 +198,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -186,6 +207,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -200,12 +222,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -215,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -224,9 +250,10 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -238,11 +265,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -255,6 +284,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -264,5 +294,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index 033910815..42e3e20b3 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:48:06
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 20:18:36
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index fa71cbd3c..ba75a74b6 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.365989                       # Nu
 sim_ticks                                365989065000                       # Number of ticks simulated
 final_tick                               365989065000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 746941                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1315244                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1730329772                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 386536                       # Number of bytes of host memory used
-host_seconds                                   211.51                       # Real time elapsed on the host
+host_inst_rate                                 696180                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1225861                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1612738645                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 388852                       # Number of bytes of host memory used
+host_seconds                                   226.94                       # Real time elapsed on the host
 sim_insts                                   157988548                       # Number of instructions simulated
 sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             51392                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           1871744                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              1923136                       # Number of bytes read from this memory
@@ -52,6 +54,8 @@ system.membus.reqLayer0.occupancy            30980000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy          270472000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
 system.cpu.numCycles                        731978130                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -86,6 +90,13 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   665.632508                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.325016                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.325016                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          784                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           23                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          715                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.382812                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         435393138                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        435393138                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    217695357                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       217695357                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     217695357                       # number of demand (read+write) hits
@@ -168,6 +179,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.589916
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.017018                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.004697                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.611630                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29708                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           78                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1693                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27875                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.906616                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         33177103                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        33177103                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            5                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1960498                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1960503                       # number of ReadReq hits
@@ -302,6 +322,14 @@ system.cpu.dcache.tags.warmup_cycle      126079701000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4076.488619                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.995236                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.995236                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          116                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1796                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2178                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         246505227                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        246505227                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     88818727                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        88818727                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     31333643                       # number of WriteReq hits
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 34784c9a2..d70753e9b 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -159,6 +159,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,9 +632,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/dist/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
index b4d96e4ea..5d8946ede 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
index cb7300a3e..0f922bcc1 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:08:48
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:41:42
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -67,4 +67,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 202349747500 because target called exit()
+Exiting @ tick 202741893000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 3188dad03..3185557ef 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.202742                       # Nu
 sim_ticks                                202741893000                       # Number of ticks simulated
 final_tick                               202741893000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  95210                       # Simulator instruction rate (inst/s)
-host_op_rate                                   107343                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               38205910                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 298452                       # Number of bytes of host memory used
-host_seconds                                  5306.56                       # Real time elapsed on the host
+host_inst_rate                                 148118                       # Simulator instruction rate (inst/s)
+host_op_rate                                   166994                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59436990                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253144                       # Number of bytes of host memory used
+host_seconds                                  3411.04                       # Real time elapsed on the host
 sim_insts                                   505237723                       # Number of instructions simulated
 sim_ops                                     569624283                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            215232                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           9270080                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              9485312                       # Number of bytes read from this memory
@@ -287,6 +289,7 @@ system.membus.reqLayer0.occupancy          1083331500                       # La
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1398080741                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups               182821881                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         143128941                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           7267602                       # Number of conditional branches incorrect
@@ -631,6 +634,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1095.413038                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.534870                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.534870                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1849                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           55                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           82                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          293                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1382                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.902832                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         229105594                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        229105594                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    114523215                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       114523215                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     114523215                       # number of demand (read+write) hits
@@ -719,6 +731,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.702196
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011015                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.113503                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.826713                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31255                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2194                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7669                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21321                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.953827                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         19093617                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        19093617                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        13491                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       804384                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         817875                       # number of ReadReq hits
@@ -878,6 +899,14 @@ system.cpu.dcache.tags.warmup_cycle        4256684250                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4057.514955                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.990604                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.990604                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           34                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2352                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1684                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         391502938                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        391502938                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    136235473                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       136235473                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     50988251                       # number of WriteReq hits
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
index 7b35bd3ad..3b7a89fcb 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@ icache_port=system.membus.slave[1]
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,9 +141,10 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -143,11 +156,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
index b9241b523..edefc9939 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:00:02
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:44:24
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
index 14e1e1ee2..d2cbe9ffb 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.290499                       # Nu
 sim_ticks                                290498967000                       # Number of ticks simulated
 final_tick                               290498967000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1591705                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1794011                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              912762441                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237748                       # Number of bytes of host memory used
-host_seconds                                   318.26                       # Real time elapsed on the host
+host_inst_rate                                2346027                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2644207                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1345327991                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 241300                       # Number of bytes of host memory used
+host_seconds                                   215.93                       # Real time elapsed on the host
 sim_insts                                   506581607                       # Number of instructions simulated
 sim_ops                                     570968167                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        2066445500                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         422852701                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           2489298201                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@ system.physmem.bw_total::total             9312824252                       # To
 system.membus.throughput                   9312824252                       # Throughput (bytes/s)
 system.membus.data_through_bus             2705365825                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index d125ef04b..cc298b9ef 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,9 +250,10 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -239,11 +265,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
index 0a37362e8..13fa82ee3 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:48:54
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:45:59
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index 3138d4062..feaf610e8 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.717366                       # Nu
 sim_ticks                                717366012000                       # Number of ticks simulated
 final_tick                               717366012000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1130634                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1274033                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1606137434                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 243872                       # Number of bytes of host memory used
-host_seconds                                   446.64                       # Real time elapsed on the host
+host_inst_rate                                1243497                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1401211                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1766466230                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251064                       # Number of bytes of host memory used
+host_seconds                                   406.10                       # Real time elapsed on the host
 sim_insts                                   504986853                       # Number of instructions simulated
 sim_ops                                     569034839                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            177280                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           8952256                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              9129536                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy          1006226000                       # La
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1283841000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -124,6 +127,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   982.663229                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.479816                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.479816                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1733                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          257                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1403                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.846191                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        1033234273                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1033234273                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    516599855                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       516599855                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     516599855                       # number of demand (read+write) hits
@@ -206,6 +218,14 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.713558
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008785                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.109054                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.831396                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31177                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          283                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3656                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27181                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951447                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18220084                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18220084                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         8751                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       743573                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         752324                       # number of ReadReq hits
@@ -340,6 +360,15 @@ system.cpu.dcache.tags.warmup_cycle       11885124000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4065.297446                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.992504                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.992504                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          343                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3546                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          165                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         363052326                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        363052326                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    122957658                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       122957658                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     53883046                       # number of WriteReq hits
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index 6c434f44b..e184df091 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -165,6 +165,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -181,6 +182,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -520,6 +522,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -536,6 +539,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,9 +632,9 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index 5d75453d9..185610e19 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
@@ -1,28 +1,15 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 02:08:50
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 20:22:33
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
  Reading the dictionary files: *********info: Increasing stack size by one page.
-**********************************info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-******
+****************************************
  58924 words stored in 3784810 bytes
 
 
@@ -34,8 +21,18 @@ Processing sentences in batch mode
 
 Echoing of input sentence turned on.
 * as had expected the party to be a success , it was a success 
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
 * do you know where John 's 
 * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
 * how fast the program is it 
 * I am wondering whether to invite to the party 
 * I gave him for his birthday it 
@@ -75,9 +72,11 @@ Echoing of input sentence turned on.
   the man with whom I play tennis is here 
   there is a dog in the park 
   this is not the man we know and love 
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
   we like to eat at restaurants , usually on weekends 
   what did John say he thought you should do 
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 458276279000 because target called exit()
+Exiting @ tick 459105675500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index d5a6aea3b..2e6ae088e 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,106 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.459341                       # Number of seconds simulated
-sim_ticks                                459340600000                       # Number of ticks simulated
-final_tick                               459340600000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.459106                       # Number of seconds simulated
+sim_ticks                                459105675500                       # Number of ticks simulated
+final_tick                               459105675500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  64463                       # Simulator instruction rate (inst/s)
-host_op_rate                                   119200                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               35810129                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 391936                       # Number of bytes of host memory used
-host_seconds                                 12827.11                       # Real time elapsed on the host
+host_inst_rate                                  97287                       # Simulator instruction rate (inst/s)
+host_op_rate                                   179895                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               54016738                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 345252                       # Number of bytes of host memory used
+host_seconds                                  8499.32                       # Real time elapsed on the host
 sim_insts                                   826877109                       # Number of instructions simulated
 sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            203008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24478016                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24681024                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       203008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          203008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18788608                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18788608                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3172                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             382469                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                385641                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          293572                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               293572                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               441955                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             53289468                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                53731423                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          441955                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             441955                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          40903434                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               40903434                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          40903434                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              441955                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            53289468                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               94634857                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        385641                       # Number of read requests accepted
-system.physmem.writeReqs                       293572                       # Number of write requests accepted
-system.physmem.readBursts                      385641                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     293572                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24669632                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     11392                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18788480                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24681024                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18788608                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      178                       # Number of DRAM read bursts serviced by the write queue
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::cpu.inst            202240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24471936                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24674176                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       202240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          202240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18788544                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18788544                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3160                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             382374                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                385534                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          293571                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               293571                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               440509                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             53303493                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                53744001                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          440509                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             440509                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          40924225                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               40924225                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          40924225                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              440509                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            53303493                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               94668226                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        385534                       # Number of read requests accepted
+system.physmem.writeReqs                       293571                       # Number of write requests accepted
+system.physmem.readBursts                      385534                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     293571                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24663936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10240                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18787328                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24674176                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18788544                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      160                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         135253                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               24057                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26446                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               24658                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24494                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               23239                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23672                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24412                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24201                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23613                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23828                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24822                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24051                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23218                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              22963                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              23780                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              24009                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18526                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               19824                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               18930                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18895                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18030                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         133980                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               24056                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26412                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               24662                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24490                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               23228                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23668                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24406                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24200                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23616                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23822                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24814                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24049                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23223                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              22960                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              23777                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              23991                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18528                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               19813                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               18933                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18904                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18032                       # Per bank write bursts
 system.physmem.perBankWrBursts::5               18409                       # Per bank write bursts
 system.physmem.perBankWrBursts::6               18982                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               18942                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18537                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               18120                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18829                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17702                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              17342                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              16954                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17718                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17830                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               18937                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18536                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               18110                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18825                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17714                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              17347                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              16962                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17712                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17808                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    459340574000                       # Total gap between requests
+system.physmem.totGap                    459105568000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  385641                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  385534                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 293572                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    380895                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4253                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       284                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 293571                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    380726                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4314                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       297                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -127,31 +129,31 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                     13203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                     13289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                     13319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                     13330                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                     13323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                     13318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                     13380                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                     13367                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                     13383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                     13400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                     13202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                     13293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                     13312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                     13323                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                     13320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                     13319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                     13374                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                     13373                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                     13375                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                     13406                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                    13420                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                    13351                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                    13361                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                    13365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                    13348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    13319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                    13359                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                    13363                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                    13367                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                    13343                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    13321                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::16                    13314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    13314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    13324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    13314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    13479                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    13297                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    13309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    13330                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    13311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    13494                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    13282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                        5                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                        3                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::26                        6                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                        3                       # What write queue length does an incoming req see
@@ -159,292 +161,295 @@ system.physmem.wrQLenPdf::28                        8                       # Wh
 system.physmem.wrQLenPdf::29                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        3                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       147621                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      294.388468                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     155.710774                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     443.499186                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64             63823     43.23%     43.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128            27954     18.94%     62.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192            12395      8.40%     70.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256             7134      4.83%     75.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320             4845      3.28%     78.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384             3604      2.44%     81.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448             2701      1.83%     82.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512             2191      1.48%     84.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576             1897      1.29%     85.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640             1561      1.06%     86.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704             2008      1.36%     88.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768             1215      0.82%     88.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832             1176      0.80%     89.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896             1069      0.72%     90.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960              885      0.60%     91.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024             912      0.62%     91.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088            1043      0.71%     92.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152            1161      0.79%     93.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216            1134      0.77%     93.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280             871      0.59%     94.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344             771      0.52%     95.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408            5235      3.55%     98.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472             297      0.20%     98.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536             223      0.15%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600             174      0.12%     99.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664             140      0.09%     99.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728              99      0.07%     99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792             107      0.07%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856              67      0.05%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920              49      0.03%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984              50      0.03%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048              49      0.03%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112              40      0.03%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176              28      0.02%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240              31      0.02%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304              21      0.01%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368              22      0.01%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432              31      0.02%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496              30      0.02%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560              18      0.01%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624              24      0.02%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688              16      0.01%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752              18      0.01%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816              20      0.01%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880              17      0.01%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944              18      0.01%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008              17      0.01%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072              21      0.01%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136              13      0.01%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200              13      0.01%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264              16      0.01%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328              15      0.01%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392               9      0.01%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456              14      0.01%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520              12      0.01%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584              17      0.01%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648              16      0.01%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712               8      0.01%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776              10      0.01%     99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840               9      0.01%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904              11      0.01%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968               6      0.00%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032              17      0.01%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096               7      0.00%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160              17      0.01%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224              18      0.01%     99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288              37      0.03%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352               5      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416               5      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480               6      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544               5      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608               4      0.00%     99.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples       147523                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      294.532839                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     155.815987                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     442.359788                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64             63790     43.24%     43.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128            27848     18.88%     62.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192            12415      8.42%     70.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256             7114      4.82%     75.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320             4845      3.28%     78.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384             3608      2.45%     81.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448             2677      1.81%     82.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512             2233      1.51%     84.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576             1891      1.28%     85.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640             1571      1.06%     86.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704             1991      1.35%     88.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768             1204      0.82%     88.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832             1205      0.82%     89.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896             1076      0.73%     90.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960              955      0.65%     91.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024             927      0.63%     91.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088            1004      0.68%     92.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152            1138      0.77%     93.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216            1120      0.76%     93.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280             845      0.57%     94.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344             784      0.53%     95.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408            5236      3.55%     98.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472             318      0.22%     98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536             229      0.16%     98.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600             157      0.11%     99.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664             117      0.08%     99.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728             103      0.07%     99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792              91      0.06%     99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856              87      0.06%     99.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920              53      0.04%     99.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984              53      0.04%     99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048              37      0.03%     99.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112              48      0.03%     99.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176              24      0.02%     99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240              28      0.02%     99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304              24      0.02%     99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368              28      0.02%     99.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432              24      0.02%     99.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496              15      0.01%     99.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560              23      0.02%     99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624              31      0.02%     99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688              20      0.01%     99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752              27      0.02%     99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816              23      0.02%     99.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880              23      0.02%     99.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944              20      0.01%     99.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008              23      0.02%     99.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072              23      0.02%     99.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136              19      0.01%     99.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200              14      0.01%     99.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264              18      0.01%     99.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328              16      0.01%     99.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392               9      0.01%     99.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456              13      0.01%     99.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520              16      0.01%     99.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584              16      0.01%     99.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648              15      0.01%     99.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712               8      0.01%     99.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776              10      0.01%     99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840               5      0.00%     99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904              11      0.01%     99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968               8      0.01%     99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032              10      0.01%     99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096               6      0.00%     99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160              14      0.01%     99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224              17      0.01%     99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288              34      0.02%     99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352               3      0.00%     99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416               7      0.00%     99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480               2      0.00%     99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544               6      0.00%     99.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608               2      0.00%     99.92% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::4672               3      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736               4      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800               1      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864               3      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928               5      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992               2      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056               8      0.01%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120               4      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184               3      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248               3      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312               6      0.00%     99.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736               5      0.00%     99.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800               6      0.00%     99.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864               1      0.00%     99.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928               6      0.00%     99.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992               5      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056               6      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120               5      0.00%     99.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184               2      0.00%     99.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248               2      0.00%     99.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312               4      0.00%     99.95% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::5376               3      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440               5      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504               5      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568               4      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632               1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696               4      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760               1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824               2      0.00%     99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440               6      0.00%     99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5504               3      0.00%     99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5568               1      0.00%     99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632               3      0.00%     99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5696               2      0.00%     99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760               4      0.00%     99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5824               4      0.00%     99.97% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::5888               6      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952               3      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016              14      0.01%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080               3      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144               2      0.00%     99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5952               4      0.00%     99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016               7      0.00%     99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080               4      0.00%     99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144               1      0.00%     99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208               2      0.00%     99.98% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::6272              19      0.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336               3      0.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6336               2      0.00%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::6528               1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552               1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         147621                       # Bytes accessed per row activation
-system.physmem.totQLat                     3824316500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               12085472750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1927315000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  6333841250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        9921.36                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    16431.77                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::7104               1      0.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         147523                       # Bytes accessed per row activation
+system.physmem.totQLat                     3823508500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               12080026000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1926870000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  6329647500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        9921.55                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    16424.69                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31353.13                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          53.71                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          40.90                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       53.73                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       40.90                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31346.24                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          53.72                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          40.92                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       53.74                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       40.92                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.74                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.42                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.32                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         0.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         9.23                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     326993                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    204419                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.83                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  69.63                       # Row buffer hit rate for writes
-system.physmem.avgGap                       676283.54                       # Average gap between requests
-system.physmem.pageHitRate                      78.26                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               5.85                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     94634857                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              178796                       # Transaction distribution
-system.membus.trans_dist::ReadResp             178796                       # Transaction distribution
-system.membus.trans_dist::Writeback            293572                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           135253                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          135253                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206845                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206845                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1335360                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1335360                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1335360                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43469632                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     43469632                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            43469632                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               43469632                       # Total data (bytes)
+system.physmem.avgWrQLen                         9.75                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     326967                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    204436                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   84.84                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  69.64                       # Row buffer hit rate for writes
+system.physmem.avgGap                       676045.04                       # Average gap between requests
+system.physmem.pageHitRate                      78.27                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               5.78                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     94668226                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              178706                       # Transaction distribution
+system.membus.trans_dist::ReadResp             178706                       # Transaction distribution
+system.membus.trans_dist::Writeback            293571                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           133980                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          133980                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206828                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206828                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1332599                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1332599                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1332599                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43462720                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     43462720                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            43462720                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               43462720                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          3391724500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          3389205500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3901051256                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3898787780                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.8                       # Layer utilization (%)
-system.cpu.branchPred.lookups               205617807                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         205617807                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           9908418                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            117215133                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               114724662                       # Number of BTB hits
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups               205604659                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         205604659                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           9906655                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            117175952                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               114700451                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.875299                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                25059559                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1805276                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.887364                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                25061463                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1805826                       # Number of incorrect RAS predictions.
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        918840117                       # number of cpu cycles simulated
+system.cpu.numCycles                        918372988                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          167454161                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1131890109                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   205617807                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          139784221                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     352321921                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                71123589                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              305412308                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                47848                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        248697                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           51                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 162055223                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2523762                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          886447009                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.375660                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.323512                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          167405307                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1131731622                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   205604659                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          139761914                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     352276692                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                71095438                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              305025706                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                47339                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        248116                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           42                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 162029256                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2531741                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          885941657                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.376715                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.323883                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                538196407     60.71%     60.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 23398337      2.64%     63.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 25267875      2.85%     66.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 27893164      3.15%     69.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 17745237      2.00%     71.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 22915160      2.59%     73.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 29437572      3.32%     77.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 26645476      3.01%     80.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                174947781     19.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                537736172     60.70%     60.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 23397075      2.64%     63.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 25259789      2.85%     66.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 27891024      3.15%     69.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 17747651      2.00%     71.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 22912562      2.59%     73.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 29424314      3.32%     77.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 26642726      3.01%     80.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                174930344     19.75%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            886447009                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.223780                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.231868                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                222604172                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             260544811                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 295377211                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              46958792                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               60962023                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2071584997                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                     1                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               60962023                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                256124443                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               115849529                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          18111                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 306710232                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             146782671                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2035392094                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 19900                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               24933273                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             106586441                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2138335278                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5151319538                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3273897775                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             39701                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            885941657                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.223879                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.232322                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                222573687                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             260132185                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 295357990                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              46939340                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               60938455                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2071381091                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                     5                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               60938455                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                256079146                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               115670707                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          18358                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 306659021                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             146575970                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2035220367                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 19921                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               24919931                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             106353414                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2138170371                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5150798156                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3273538468                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             41295                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                524294424                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1242                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1171                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 346564705                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            495938130                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           194456766                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         195343621                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         54992684                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1975627132                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               13244                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1772183771                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            484863                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       441729805                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    735457697                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          12692                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     886447009                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.999199                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.882883                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                524129517                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1246                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1179                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 346542949                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            495881862                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           194416479                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         195473768                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         54732552                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1975446731                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               13521                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1772053501                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            482535                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       441556981                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    735252947                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          12969                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     885941657                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.000192                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.883038                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           269548828     30.41%     30.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           152175288     17.17%     47.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           137113127     15.47%     63.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           132050060     14.90%     77.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            91550725     10.33%     88.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            55998430      6.32%     94.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            34403840      3.88%     98.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            11839729      1.34%     99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1766982      0.20%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           269231258     30.39%     30.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           151900240     17.15%     47.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           137366514     15.51%     63.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           131748871     14.87%     77.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            91701810     10.35%     88.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            55961984      6.32%     94.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            34425337      3.89%     98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            11840706      1.34%     99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1764937      0.20%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       886447009                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       885941657                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 4936288     32.45%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                7665302     50.39%     82.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2609145     17.15%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 4931859     32.39%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                7680982     50.45%     82.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2612006     17.16%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2622898      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1165798232     65.78%     65.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               353842      0.02%     65.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               3880856      0.22%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2622482      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1165712605     65.78%     65.93% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               353084      0.02%     65.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               3880807      0.22%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   5      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.17% # Type of FU issued
@@ -471,84 +476,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.17% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            429305841     24.22%     90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           170222097      9.61%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            429261253     24.22%     90.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           170223265      9.61%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1772183771                       # Type of FU issued
-system.cpu.iq.rate                           1.928718                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    15210735                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.008583                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4446495646                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2417577635                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1744952561                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               14503                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              50594                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         3428                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1784764794                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    6814                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        172654482                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1772053501                       # Type of FU issued
+system.cpu.iq.rate                           1.929558                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    15224847                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008592                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4445741046                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2417220510                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1744818779                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               14995                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              52000                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         3560                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1784648801                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    7065                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        172668148                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    111836934                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       389891                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       330016                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     45296580                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    111780722                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       387016                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       326982                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     45256293                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        14646                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads        15018                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked           570                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               60962023                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                68066484                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               7196875                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1975640376                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            789853                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             495939091                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            194456766                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               3282                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                4474777                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 82775                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         330016                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        5907886                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4422310                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             10330196                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1753064930                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             424170565                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          19118841                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               60938455                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                67998417                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               7163340                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1975460252                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            795198                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             495882879                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            194416479                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               3400                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                4461902                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 83950                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         326982                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        5904539                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4423611                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             10328150                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1752928715                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             424128579                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          19124786                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    590955910                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                167475793                       # Number of branches executed
-system.cpu.iew.exec_stores                  166785345                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.907911                       # Inst execution rate
-system.cpu.iew.wb_sent                     1749812928                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1744955989                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1325071537                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1945900521                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    590915769                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                167467646                       # Number of branches executed
+system.cpu.iew.exec_stores                  166787190                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.908733                       # Inst execution rate
+system.cpu.iew.wb_sent                     1749675549                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1744822339                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1324948168                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1945614075                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.899086                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.680955                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.899906                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.680992                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       446680078                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       446501460                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           9936737                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    825484986                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.852231                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.435254                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           9934679                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    825003202                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.853312                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.435859                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    333347760     40.38%     40.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    193315332     23.42%     63.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     63291763      7.67%     71.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     92551196     11.21%     82.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     24974559      3.03%     85.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     27516320      3.33%     89.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      9293108      1.13%     90.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     11361813      1.38%     91.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     69833135      8.46%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    333018307     40.37%     40.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    193164035     23.41%     63.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     63275385      7.67%     71.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     92552193     11.22%     82.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     24927805      3.02%     85.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     27507260      3.33%     89.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      9364368      1.14%     90.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     11367203      1.38%     91.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     69826646      8.46%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    825484986                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    825003202                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -559,228 +564,245 @@ system.cpu.commit.branches                  149758583                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1526605509                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              69833135                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              69826646                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2731320630                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4012461124                       # The number of ROB writes
-system.cpu.timesIdled                         3340699                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        32393108                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   2730666717                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4012080782                       # The number of ROB writes
+system.cpu.timesIdled                         3354849                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        32431331                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
 system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             826877109                       # Number of Instructions Simulated
-system.cpu.cpi                               1.111217                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.111217                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.899914                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.899914                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2716389897                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1420532102                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      3421                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       19                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 597244921                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                405448259                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               964724023                       # number of misc regfile reads
+system.cpu.cpi                               1.110652                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.110652                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.900372                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.900372                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2716202384                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1420402354                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      3547                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       23                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 597198676                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                405403172                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               964659775                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               697845146                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1906044                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1906043                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2330771                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq       136656                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp       136656                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       771758                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       771758                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       150484                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7672451                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7822935                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       439424                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311357120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      311796544                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         311796544                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus      8752064                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     4906973310                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               697995780                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1904573                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1904572                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2330749                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq       135378                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp       135378                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       771770                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       771770                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       149099                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7669617                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7818716                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       435968                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311347520                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      311783488                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         311783488                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus      8670336                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     4905098758                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     215891495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     213898487                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3953569925                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3952694158                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              5335                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1037.583647                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           161907582                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6916                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          23410.581550                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              5304                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1036.579952                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           161882998                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6874                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          23550.043352                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1037.583647                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.506633                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.506633                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    161909622                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       161909622                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     161909622                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        161909622                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    161909622                       # number of overall hits
-system.cpu.icache.overall_hits::total       161909622                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       145600                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        145600                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       145600                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         145600                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       145600                       # number of overall misses
-system.cpu.icache.overall_misses::total        145600                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    941474740                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    941474740                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    941474740                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    941474740                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    941474740                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    941474740                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    162055222                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    162055222                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    162055222                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    162055222                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    162055222                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    162055222                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000898                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000898                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000898                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000898                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000898                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000898                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6466.172665                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  6466.172665                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  6466.172665                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  6466.172665                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  6466.172665                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  6466.172665                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          250                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          170                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    41.666667                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          170                       # average number of cycles each access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1036.579952                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.506143                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.506143                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1570                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          248                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1211                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.766602                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         324200798                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        324200798                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    161884991                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       161884991                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     161884991                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        161884991                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    161884991                       # number of overall hits
+system.cpu.icache.overall_hits::total       161884991                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       144265                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        144265                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       144265                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         144265                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       144265                       # number of overall misses
+system.cpu.icache.overall_misses::total        144265                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    939571727                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    939571727                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    939571727                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    939571727                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    939571727                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    939571727                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    162029256                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    162029256                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    162029256                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    162029256                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    162029256                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    162029256                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000890                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000890                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000890                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000890                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000890                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000890                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6512.818265                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  6512.818265                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  6512.818265                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  6512.818265                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  6512.818265                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  6512.818265                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          329                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    41.125000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1982                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1982                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1982                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1982                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1982                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1982                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       143618                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       143618                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       143618                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       143618                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       143618                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       143618                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    562974254                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    562974254                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    562974254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    562974254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    562974254                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    562974254                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000886                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000886                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000886                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000886                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000886                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000886                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3919.942166                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3919.942166                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3919.942166                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  3919.942166                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3919.942166                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  3919.942166                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1978                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1978                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1978                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1978                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1978                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1978                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       142287                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       142287                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       142287                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       142287                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       142287                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       142287                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    558890013                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    558890013                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    558890013                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    558890013                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    558890013                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    558890013                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000878                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000878                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000878                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000878                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000878                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000878                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3927.906365                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3927.906365                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3927.906365                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  3927.906365                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3927.906365                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  3927.906365                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           352959                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29669.713018                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3697218                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           385325                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             9.595064                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           352852                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29667.815296                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3696724                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           385211                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             9.596621                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle     199249645000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21121.996968                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   224.213504                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8323.502546                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.644592                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.006842                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.254013                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.905448                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         3694                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1586802                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1590496                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2330771                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2330771                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1427                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1427                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       564889                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       564889                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3694                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2151691                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2155385                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3694                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2151691                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2155385                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3173                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       175624                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       178797                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data       135229                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total       135229                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206869                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206869                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3173                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       382493                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        385666                       # number of demand (read+write) misses
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-system.cpu.l2cache.overall_misses::cpu.data       382493                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       385666                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    242389500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  13196439955                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  13438829455                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      6577717                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      6577717                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  15144418976                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  15144418976                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    242389500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  28340858931                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  28583248431                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    242389500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  28340858931                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  28583248431                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         6867                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1762426                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1769293                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2330771                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2330771                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data       136656                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total       136656                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       771758                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       771758                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         6867                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2534184                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2541051                       # number of demand (read+write) accesses
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -789,168 +811,176 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151743                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.463966                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150904                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151743                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63894.574502                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62360.161781                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62387.302736                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.451711                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.451711                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60528.950632                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60528.950632                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63894.574502                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61369.595593                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61390.296543                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63894.574502                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61369.595593                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61390.296543                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           2530088                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4088.247279                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           395994774                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2534184                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            156.261256                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           2529960                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4088.243311                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           395939715                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2534056                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            156.247421                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        1794365000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4088.247279                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998107                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998107                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    247245006                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       247245006                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148235012                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148235012                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     395480018                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        395480018                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    395480018                       # number of overall hits
-system.cpu.dcache.overall_hits::total       395480018                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2882280                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2882280                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       925190                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       925190                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3807470                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3807470                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3807470                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3807470                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  58083545125                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  58083545125                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  26852968678                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  26852968678                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  84936513803                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  84936513803                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  84936513803                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  84936513803                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    250127286                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    250127286                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data  4088.243311                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998106                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998106                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          739                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3316                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         801001196                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        801001196                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    247190433                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       247190433                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148236290                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148236290                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     395426723                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        395426723                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    395426723                       # number of overall hits
+system.cpu.dcache.overall_hits::total       395426723                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2882935                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2882935                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       923912                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       923912                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3806847                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3806847                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3806847                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3806847                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  58045368359                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  58045368359                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  26823619163                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  26823619163                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  84868987522                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  84868987522                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  84868987522                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  84868987522                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    250073368                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    250073368                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    399287488                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    399287488                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    399287488                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    399287488                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011523                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.011523                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006203                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006203                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009536                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009536                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009536                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009536                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20151.943991                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 20151.943991                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29024.274666                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29024.274666                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22307.861599                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22307.861599                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22307.861599                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22307.861599                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         5821                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    399233570                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    399233570                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    399233570                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    399233570                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011528                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.011528                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006194                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006194                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009535                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009535                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009535                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009535                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20134.123162                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20134.123162                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29032.655884                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29032.655884                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22293.774224                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22293.774224                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22293.774224                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22293.774224                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         6982                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               669                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               660                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     8.701046                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.578788                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2330771                       # number of writebacks
-system.cpu.dcache.writebacks::total           2330771                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1119584                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1119584                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        17046                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        17046                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1136630                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1136630                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1136630                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1136630                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1762696                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1762696                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       908144                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       908144                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2670840                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2670840                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2670840                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2670840                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30862153254                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  30862153254                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  24727931821                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  24727931821                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  55590085075                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  55590085075                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  55590085075                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  55590085075                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007047                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007047                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006088                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006088                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006689                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006689                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006689                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006689                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17508.494519                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17508.494519                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27229.086820                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27229.086820                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20813.708449                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20813.708449                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20813.708449                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20813.708449                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2330749                       # number of writebacks
+system.cpu.dcache.writebacks::total           2330749                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1120394                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1120394                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        17019                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        17019                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1137413                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1137413                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1137413                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1137413                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1762541                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1762541                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       906893                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       906893                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2669434                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2669434                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2669434                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2669434                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30851541255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  30851541255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  24700633087                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  24700633087                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  55552174342                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  55552174342                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  55552174342                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  55552174342                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007048                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007048                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006080                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006080                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006686                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006686                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006686                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006686                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.013385                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.013385                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27236.546193                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27236.546193                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20810.469314                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20810.469314                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20810.469314                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20810.469314                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
index 397d5a34d..bcd42cfa4 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -76,16 +81,19 @@ icache_port=system.membus.slave[1]
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
@@ -93,6 +101,7 @@ port=system.membus.slave[4]
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -103,22 +112,26 @@ pio=system.membus.master[1]
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -128,9 +141,10 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -142,11 +156,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -159,6 +175,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -168,5 +185,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
index abce0a0d4..cbb107c47 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:44:23
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 20:48:32
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 87dac48c4..4df869dc7 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.885229                       # Nu
 sim_ticks                                885229328000                       # Number of ticks simulated
 final_tick                               885229328000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1293065                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2391022                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1384315331                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 251216                       # Number of bytes of host memory used
-host_seconds                                   639.47                       # Real time elapsed on the host
+host_inst_rate                                1633857                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3021184                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1749156833                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 252248                       # Number of bytes of host memory used
+host_seconds                                   506.09                       # Real time elapsed on the host
 sim_insts                                   826877110                       # Number of instructions simulated
 sim_ops                                    1528988702                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        8546776520                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        2285655658                       # Number of bytes read from this memory
 system.physmem.bytes_read::total          10832432178                       # Number of bytes read from this memory
@@ -36,6 +38,8 @@ system.physmem.bw_total::total            13357308966                       # To
 system.membus.throughput                  13357308966                       # Throughput (bytes/s)
 system.membus.data_through_bus            11824281640                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
 system.cpu.numCycles                       1770458657                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index 3a3bc324c..bd4e435a1 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -69,6 +74,7 @@ icache_port=system.cpu.icache.cpu_side
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dcache]
 type=BaseCache
@@ -76,6 +82,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -84,6 +91,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -98,18 +106,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
@@ -120,6 +132,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -128,6 +141,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -142,12 +156,15 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -158,16 +175,19 @@ pio=system.membus.master[1]
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
@@ -178,6 +198,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -186,6 +207,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -200,12 +222,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -215,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -224,9 +250,10 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -238,11 +265,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -255,6 +284,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -264,5 +294,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
index 59b399b0b..530ac97a0 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:41:23
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 20:57:08
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index 43f2a7587..c65900aab 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  1.647873                       # Nu
 sim_ticks                                1647872849000                       # Number of ticks simulated
 final_tick                               1647872849000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 788676                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1458350                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1571742015                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 258676                       # Number of bytes of host memory used
-host_seconds                                  1048.44                       # Real time elapsed on the host
+host_inst_rate                                 782951                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1447764                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1560332529                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 260992                       # Number of bytes of host memory used
+host_seconds                                  1056.10                       # Real time elapsed on the host
 sim_insts                                   826877110                       # Number of instructions simulated
 sim_ops                                    1528988702                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            120704                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          24272448                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             24393152                       # Number of bytes read from this memory
@@ -52,6 +54,8 @@ system.membus.reqLayer0.occupancy          3011737000                       # La
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         3430300500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
 system.cpu.numCycles                       3295745698                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -86,6 +90,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   881.356491                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.430350                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.430350                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1561                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            8                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1507                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.762207                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        2136696946                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       2136696946                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst   1068344252                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1068344252                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1068344252                       # number of demand (read+write) hits
@@ -168,6 +181,14 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.642129
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004265                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.247355                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.893750                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32355                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         8220                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        24069                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987396                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         39930218                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        39930218                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst          928                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1554848                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1555776                       # number of ReadReq hits
@@ -302,6 +323,15 @@ system.cpu.dcache.tags.warmup_cycle        8211724000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4086.415783                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997660                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997660                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           29                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         4038                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1069043234                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1069043234                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    382374772                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       382374772                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    148369158                       # number of WriteReq hits
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
index a92131062..c27165d1c 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -56,6 +60,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fetchBuffSize=4
 function_trace=false
 function_trace_start=0
@@ -90,6 +95,7 @@ BTBTagSize=16
 RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
+eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
@@ -105,6 +111,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -113,6 +120,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -127,11 +135,14 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -140,6 +151,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -148,6 +160,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -162,17 +175,23 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -181,6 +200,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -189,6 +209,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -203,12 +224,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -218,6 +242,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -227,7 +252,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -241,11 +267,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -265,6 +293,7 @@ conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -276,17 +305,21 @@ static_backend_latency=10000
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
index 860580eeb..abe1622a9 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
@@ -49,4 +49,3 @@ Writing to chair.cook.ppm
 13  8  14
 14  8  14
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
index 3f1389dac..8e653912b 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 09:53:14
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:48:27
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -11,4 +11,4 @@ info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.133333
-Exiting @ tick 139916242500 because target called exit()
+Exiting @ tick 139926186500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
index 0feb1e331..eb5995295 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.139926                       # Nu
 sim_ticks                                139926186500                       # Number of ticks simulated
 final_tick                               139926186500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 122800                       # Simulator instruction rate (inst/s)
-host_op_rate                                   122800                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               43101138                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 261428                       # Number of bytes of host memory used
-host_seconds                                  3246.46                       # Real time elapsed on the host
+host_inst_rate                                 138827                       # Simulator instruction rate (inst/s)
+host_op_rate                                   138827                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               48726388                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236592                       # Number of bytes of host memory used
+host_seconds                                  2871.67                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            214976                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            254016                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               468992                       # Number of bytes read from this memory
@@ -257,6 +259,7 @@ system.membus.reqLayer0.occupancy             8743500                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           68145750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                53489673                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          30685396                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          15149659                       # Number of conditional branches incorrect
@@ -368,6 +371,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1830.939408                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.894013                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.894013                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1928                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          322                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1366                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.941406                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          97226551                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         97226551                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     48606790                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        48606790                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      48606790                       # number of demand (read+write) hits
@@ -476,6 +488,14 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.011308
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088768                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.019152                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.119227                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4717                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          564                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3928                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.143951                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            77554                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           77554                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst          544                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          123                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total            667                       # number of ReadReq hits
@@ -608,6 +628,15 @@ system.cpu.dcache.tags.warmup_cycle                 0                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  3284.890275                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.801975                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.801975                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3388                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          216                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3109                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.827148                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         336554588                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336554588                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     94753181                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        94753181                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     73501074                       # number of WriteReq hits
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 427d7de3e..0f18e6f39 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -159,6 +159,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -504,6 +506,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -520,6 +523,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -529,6 +533,7 @@ eventq_index=0
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -550,6 +555,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -566,6 +572,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -592,7 +599,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/dist/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
index 860580eeb..abe1622a9 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
@@ -49,4 +49,3 @@ Writing to chair.cook.ppm
 13  8  14
 14  8  14
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
index 58c019f98..987d9ef76 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 16 2013 01:34:33
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:48:27
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -11,4 +11,4 @@ info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.066667
-Exiting @ tick 77521581000 because target called exit()
+Exiting @ tick 77516381000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 68636d517..39e558e65 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.077516                       # Nu
 sim_ticks                                 77516381000                       # Number of ticks simulated
 final_tick                                77516381000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 154118                       # Simulator instruction rate (inst/s)
-host_op_rate                                   154118                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               31808931                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 282024                       # Number of bytes of host memory used
-host_seconds                                  2436.94                       # Real time elapsed on the host
+host_inst_rate                                 222910                       # Simulator instruction rate (inst/s)
+host_op_rate                                   222910                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               46007212                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236600                       # Number of bytes of host memory used
+host_seconds                                  1684.87                       # Real time elapsed on the host
 sim_insts                                   375574808                       # Number of instructions simulated
 sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            221184                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            255424                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               476608                       # Number of bytes read from this memory
@@ -250,6 +252,7 @@ system.membus.reqLayer0.occupancy             9290500                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           69562000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                50307155                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          29267262                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           1212205                       # Number of conditional branches incorrect
@@ -582,6 +585,14 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1831.580097                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.894326                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.894326                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1928                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          336                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1334                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.941406                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         100598535                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        100598535                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     50291612                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        50291612                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      50291612                       # number of demand (read+write) hits
@@ -670,6 +681,14 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.011362
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.090728                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.020184                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.122275                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4855                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          149                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           96                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          579                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4031                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148163                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            79325                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           79325                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst          613                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          131                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total            744                       # number of ReadReq hits
@@ -802,6 +821,15 @@ system.cpu.dcache.tags.warmup_cycle                 0                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  3295.992263                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.804686                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.804686                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3402                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          215                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3117                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.830566                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         320069754                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        320069754                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     86510267                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        86510267                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     73500882                       # number of WriteReq hits
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index 9894abc48..edbb4f97d 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,26 @@ icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +108,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +123,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +142,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +152,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
index 28eb1122e..abe1622a9 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
@@ -1,4 +1,3 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
@@ -50,4 +49,3 @@ Writing to chair.cook.ppm
 13  8  14
 14  8  14
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
index b09a5533b..e4df23735 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 09:53:14
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:48:27
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index 721e957fa..2fdd2b1a5 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.199332                       # Nu
 sim_ticks                                199332411500                       # Number of ticks simulated
 final_tick                               199332411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1715563                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1715563                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              857781835                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222488                       # Number of bytes of host memory used
-host_seconds                                   232.38                       # Real time elapsed on the host
+host_inst_rate                                3310187                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3310187                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1655094150                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226700                       # Number of bytes of host memory used
+host_seconds                                   120.44                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        1594658604                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         662449271                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           2257107875                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@ system.physmem.bw_total::total            13793364824                       # To
 system.membus.throughput                  13793364824                       # Throughput (bytes/s)
 system.membus.data_through_bus             2749464673                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
index 17feee0a3..b264a599b 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -147,6 +165,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +174,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +217,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +232,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +251,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +261,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
index 860580eeb..abe1622a9 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
@@ -49,4 +49,3 @@ Writing to chair.cook.ppm
 13  8  14
 14  8  14
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
index b94ac7377..ab67caf1c 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 09:53:14
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:48:27
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 3ed6163c0..143a0b323 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.567335                       # Nu
 sim_ticks                                567335093000                       # Number of ticks simulated
 final_tick                               567335093000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1598767                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1598767                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2275187152                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229960                       # Number of bytes of host memory used
-host_seconds                                   249.36                       # Real time elapsed on the host
+host_inst_rate                                1478735                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1478735                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2104370306                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235572                       # Number of bytes of host memory used
+host_seconds                                   269.60                       # Real time elapsed on the host
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            205120                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            254016                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               459136                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy             7174000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           64566000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -106,6 +109,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1795.138964                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.876533                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.876533                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1904                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          142                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          251                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1375                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.929688                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         797333005                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        797333005                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    398660993                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       398660993                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     398660993                       # number of demand (read+write) hits
@@ -188,6 +200,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.011339
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084548                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.019241                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.115127                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4566                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           75                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          497                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3787                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.139343                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            75560                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           75560                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst          468                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          123                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total            591                       # number of ReadReq hits
@@ -320,6 +341,15 @@ system.cpu.dcache.tags.warmup_cycle                 0                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  3288.930576                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.802962                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.802962                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3388                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          210                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3112                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.827148                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         336554592                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336554592                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     94753540                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        94753540                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     73517528                       # number of WriteReq hits
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index 8cc45b24c..9e26a822b 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -159,6 +159,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,7 +632,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/dist/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
index e8096c4c9..cce4a65d9 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
@@ -46,4 +46,3 @@ Writing to chair.cook.ppm
 12  8  14
 13  8  14
 14  8  14
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index d3e872fc3..704a64531 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:05:47
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:48:11
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -13,4 +13,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.060000
-Exiting @ tick 68375005500 because target called exit()
+Exiting @ tick 68509635500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 356503ef7..d1e8937b6 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.068510                       # Nu
 sim_ticks                                 68509635500                       # Number of ticks simulated
 final_tick                                68509635500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 105106                       # Simulator instruction rate (inst/s)
-host_op_rate                                   134373                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               26372946                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303620                       # Number of bytes of host memory used
-host_seconds                                  2597.72                       # Real time elapsed on the host
+host_inst_rate                                 157844                       # Simulator instruction rate (inst/s)
+host_op_rate                                   201796                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               39605771                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257252                       # Number of bytes of host memory used
+host_seconds                                  1729.79                       # Real time elapsed on the host
 sim_insts                                   273036725                       # Number of instructions simulated
 sim_ops                                     349064449                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            194560                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            272384                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               466944                       # Number of bytes read from this memory
@@ -257,6 +259,7 @@ system.membus.reqLayer0.occupancy             8937500                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           67899498                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                35425567                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          21222314                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           1660593                       # Number of conditional branches incorrect
@@ -602,6 +605,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1848.251388                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.902466                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.902466                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1890                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           95                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          206                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1526                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.922852                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          75234453                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         75234453                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     37591948                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        37591948                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      37591948                       # number of demand (read+write) hits
@@ -690,6 +702,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.011566
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.085036                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.023692                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.120294                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5394                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1235                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4014                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.164612                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           180292                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          180292                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        12803                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          301                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          13104                       # number of ReadReq hits
@@ -845,6 +866,15 @@ system.cpu.dcache.tags.warmup_cycle                 0                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  3102.941006                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.757554                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.757554                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3197                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          684                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2446                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.780518                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         342019754                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        342019754                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     88929043                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        88929043                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     82031381                       # number of WriteReq hits
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
index 1c8f49cef..098c10a60 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@ icache_port=system.membus.slave[1]
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,7 +141,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -143,11 +156,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
index bf930ad43..a25196116 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
@@ -45,4 +45,3 @@ Writing to chair.cook.ppm
 12  8  14
 13  8  14
 14  8  14
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
index 9c8ccea96..b3ebb4d02 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:21:07
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:52:31
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 590c33ff6..02fd51087 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.212344                       # Nu
 sim_ticks                                212344043000                       # Number of ticks simulated
 final_tick                               212344043000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1381175                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1765765                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1074152891                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241892                       # Number of bytes of host memory used
-host_seconds                                   197.69                       # Real time elapsed on the host
+host_inst_rate                                1679583                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2147266                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1306228104                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246496                       # Number of bytes of host memory used
+host_seconds                                   162.56                       # Real time elapsed on the host
 sim_insts                                   273037663                       # Number of instructions simulated
 sim_ops                                     349065399                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        1394641404                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         480709268                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           1875350672                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@ system.physmem.bw_total::total            10715621794                       # To
 system.membus.throughput                  10715621794                       # Throughput (bytes/s)
 system.membus.data_through_bus             2275398455                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
index f3f7cd9b4..aa5380744 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,7 +250,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -239,11 +265,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
index bf930ad43..a25196116 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
@@ -45,4 +45,3 @@ Writing to chair.cook.ppm
 12  8  14
 13  8  14
 14  8  14
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
index b54aa45d0..32b55c30c 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:19:15
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:52:55
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index 313988369..5bfa9270c 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.525834                       # Nu
 sim_ticks                                525834342000                       # Number of ticks simulated
 final_tick                               525834342000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 414348                       # Simulator instruction rate (inst/s)
-host_op_rate                                   529728                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              798851724                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 248008                       # Number of bytes of host memory used
-host_seconds                                   658.24                       # Real time elapsed on the host
+host_inst_rate                                 870200                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1112519                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1677723175                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 255236                       # Number of bytes of host memory used
+host_seconds                                   313.42                       # Real time elapsed on the host
 sim_insts                                   272739283                       # Number of instructions simulated
 sim_ops                                     348687122                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            166976                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            270272                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               437248                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy             6832000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           61488000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -116,6 +119,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1765.993223                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.862301                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.862301                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1807                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          161                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1524                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.882324                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         697336303                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        697336303                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    348644747                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       348644747                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     348644747                       # number of demand (read+write) hits
@@ -198,6 +210,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.010425
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073499                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.022513                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.106437                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4882                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           46                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1232                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3543                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148987                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           176386                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          176386                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        12994                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          239                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          13233                       # number of ReadReq hits
@@ -330,6 +351,15 @@ system.cpu.dcache.tags.warmup_cycle                 0                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  3078.412981                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.751566                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.751566                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           11                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          677                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2428                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.768066                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         353296632                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        353296632                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     94570004                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        94570004                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     82049805                       # number of WriteReq hits
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 3613fc19c..328cf1d6a 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -159,6 +159,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -504,6 +506,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -520,6 +523,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -529,6 +533,7 @@ eventq_index=0
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -550,6 +555,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -566,6 +572,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -592,7 +599,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/dist/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
index ca52b457d..b38cab2f9 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
@@ -4,4 +4,3 @@ warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(0, 1, ...)
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index 091ca3b5c..722b9bf34 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 15 2013 18:56:50
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:50:38
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -1387,4 +1385,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 631883288500 because target called exit()
+Exiting @ tick 631518097500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 2a6478fe5..130b22828 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.631518                       # Nu
 sim_ticks                                631518097500                       # Number of ticks simulated
 final_tick                               631518097500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 116160                       # Simulator instruction rate (inst/s)
-host_op_rate                                   116160                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               40238771                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 286040                       # Number of bytes of host memory used
-host_seconds                                 15694.27                       # Real time elapsed on the host
+host_inst_rate                                 171044                       # Simulator instruction rate (inst/s)
+host_op_rate                                   171044                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59250964                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240608                       # Number of bytes of host memory used
+host_seconds                                 10658.36                       # Real time elapsed on the host
 sim_insts                                  1823043370                       # Number of instructions simulated
 sim_ops                                    1823043370                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            176128                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          30295488                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             30471616                       # Number of bytes read from this memory
@@ -314,6 +316,7 @@ system.membus.reqLayer0.occupancy          1230652000                       # La
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         4488013500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups               388926557                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         255987580                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          25808786                       # Number of conditional branches incorrect
@@ -646,6 +649,14 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1658.001589                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.809571                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.809571                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1713                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1567                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.836426                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         789856696                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        789856696                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    394910393                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       394910393                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     394910393                       # number of demand (read+write) hits
@@ -734,6 +745,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.040675
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001074                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.955840                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.997589                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32736                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          188                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          505                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5021                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26866                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         13650820                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13650820                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         7273                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1053738                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1061011                       # number of ReadReq hits
@@ -868,6 +888,15 @@ system.cpu.dcache.tags.warmup_cycle         408904250                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4094.588575                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999655                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999655                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           86                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          284                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          969                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2365                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          392                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1343398986                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1343398986                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    458212871                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       458212871                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    209732941                       # number of WriteReq hits
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index d4071b647..3b24ee769 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,26 @@ icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +108,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +123,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +142,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +152,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
index 1c6544a2e..b38cab2f9 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
@@ -1,8 +1,6 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(0, 1, ...)
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index 0011f9cf8..385d89721 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 09:53:14
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:53:08
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index e66382473..65e54342a 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  1.004711                       # Nu
 sim_ticks                                1004710587000                       # Number of ticks simulated
 final_tick                               1004710587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3493388                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3493388                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1747070946                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225488                       # Number of bytes of host memory used
-host_seconds                                   575.08                       # Real time elapsed on the host
+host_inst_rate                                3768106                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3768106                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1884459398                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229696                       # Number of bytes of host memory used
+host_seconds                                   533.16                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        8037684280                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        3569416716                       # Number of bytes read from this memory
 system.physmem.bytes_read::total          11607100996                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@ system.physmem.bw_total::total            13131370496                       # To
 system.membus.throughput                  13131370496                       # Throughput (bytes/s)
 system.membus.data_through_bus            13193226959                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index d6223b426..34c972fc4 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -147,6 +165,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +174,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +217,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +232,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +251,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +261,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
index ca52b457d..b38cab2f9 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
@@ -4,4 +4,3 @@ warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(0, 1, ...)
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index a19734d3d..f48beb892 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 09:53:14
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:02:12
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 421623453..068ca2e0b 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  2.769740                       # Nu
 sim_ticks                                2769739533000                       # Number of ticks simulated
 final_tick                               2769739533000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 892879                       # Simulator instruction rate (inst/s)
-host_op_rate                                   892879                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1230989339                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233984                       # Number of bytes of host memory used
-host_seconds                                  2250.01                       # Real time elapsed on the host
+host_inst_rate                                1540787                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1540787                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2124243508                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238596                       # Number of bytes of host memory used
+host_seconds                                  1303.87                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            137792                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          30284544                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             30422336                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy          1077521000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         4278141000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -114,6 +117,14 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1478.418050                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.721884                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.721884                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1550                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           72                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1428                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.756836                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        4018852738                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       4018852738                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst   2009410475                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      2009410475                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    2009410475                       # number of demand (read+write) hits
@@ -196,6 +207,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.039688
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000809                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.957636                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.998134                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32732                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          174                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          116                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1143                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31199                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998901                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         13642206                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13642206                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         8443                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1051869                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1060312                       # number of ReadReq hits
@@ -330,6 +350,15 @@ system.cpu.dcache.tags.warmup_cycle        1041395000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4095.197836                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999804                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999804                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          160                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          466                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          999                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2416                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1445259988                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1445259988                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    509611834                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       509611834                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    210722944                       # number of WriteReq hits
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index cbb921be0..116b954da 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -159,6 +159,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,7 +632,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
index cba73e085..2de5e2759 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: fcntl64(3, 2) passed through to host
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
index 3ba2de45d..f17e243b1 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:40:46
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:55:24
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 640648369500 because target called exit()
+Exiting @ tick 629535413500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 6310afb8f..f4aa63ff2 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.629535                       # Nu
 sim_ticks                                629535413500                       # Number of ticks simulated
 final_tick                               629535413500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  71307                       # Simulator instruction rate (inst/s)
-host_op_rate                                    97111                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               32426577                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303200                       # Number of bytes of host memory used
-host_seconds                                 19414.18                       # Real time elapsed on the host
+host_inst_rate                                 111054                       # Simulator instruction rate (inst/s)
+host_op_rate                                   151240                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               50501117                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257896                       # Number of bytes of host memory used
+host_seconds                                 12465.77                       # Real time elapsed on the host
 sim_insts                                  1384370590                       # Number of instructions simulated
 sim_ops                                    1885325342                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            155136                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          30242496                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             30397632                       # Number of bytes read from this memory
@@ -305,6 +307,7 @@ system.membus.reqLayer0.occupancy          1215450500                       # La
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         4442867738                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups               438247561                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         350864310                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          30620817                       # Number of conditional branches incorrect
@@ -650,6 +653,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1641.273486                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.801403                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.801403                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1685                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1551                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.822754                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         669498564                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        669498564                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    334702534                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       334702534                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     334702534                       # number of demand (read+write) hits
@@ -738,6 +750,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.040208
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001578                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.955470                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.997256                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32748                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          154                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          507                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5020                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26968                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999390                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         13848752                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13848752                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        22592                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1058063                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1080655                       # number of ReadReq hits
@@ -897,6 +918,15 @@ system.cpu.dcache.tags.warmup_cycle         400505250                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4094.376677                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999604                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999604                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          977                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2409                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          402                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1949922006                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1949922006                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    695282689                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       695282689                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    276093049                       # number of WriteReq hits
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index 583a974bb..879581bbb 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@ icache_port=system.membus.slave[1]
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,7 +141,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -143,11 +156,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
index cba73e085..2de5e2759 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: fcntl64(3, 2) passed through to host
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
index 2dca8a365..6d065fef8 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:31:40
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:58:19
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index ae323b307..982d92f29 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.945613                       # Nu
 sim_ticks                                945613126000                       # Number of ticks simulated
 final_tick                               945613126000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1181509                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1609052                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              807039161                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242488                       # Number of bytes of host memory used
-host_seconds                                  1171.71                       # Real time elapsed on the host
+host_inst_rate                                1817390                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2475033                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1241382789                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247108                       # Number of bytes of host memory used
+host_seconds                                   761.74                       # Real time elapsed on the host
 sim_insts                                  1384381606                       # Number of instructions simulated
 sim_ops                                    1885336358                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        5561086004                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        2464405274                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           8025491278                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@ system.physmem.bw_total::total             9675679644                       # To
 system.membus.throughput                   9675679644                       # Throughput (bytes/s)
 system.membus.data_through_bus             9149449674                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index e7d15bd7c..0bdfc6610 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,7 +250,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -239,11 +265,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
index cba73e085..2de5e2759 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: fcntl64(3, 2) passed through to host
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
index 15b548e96..973b4e1bf 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:11:37
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:11:12
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 65ea4c6ca..ecd5fda89 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  2.326119                       # Nu
 sim_ticks                                2326118592000                       # Number of ticks simulated
 final_tick                               2326118592000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 481372                       # Simulator instruction rate (inst/s)
-host_op_rate                                   653016                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              810455855                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 248632                       # Number of bytes of host memory used
-host_seconds                                  2870.14                       # Real time elapsed on the host
+host_inst_rate                                 968971                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1314478                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1631393565                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 255816                       # Number of bytes of host memory used
+host_seconds                                  1425.85                       # Real time elapsed on the host
 sim_insts                                  1381604339                       # Number of instructions simulated
 sim_ops                                    1874244941                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            113472                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          30232512                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             30345984                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy          1069047000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         4267404000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -124,6 +127,13 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1392.317060                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.679842                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.679842                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1439                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1339                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.702637                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        2780562807                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       2780562807                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst   1390251699                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1390251699                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1390251699                       # number of demand (read+write) hits
@@ -206,6 +216,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.039616
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000923                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.957169                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.997708                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32743                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          144                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1387                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31024                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999237                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         13744605                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13744605                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        18030                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1054583                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1072613                       # number of ReadReq hits
@@ -340,6 +359,15 @@ system.cpu.dcache.tags.warmup_cycle         991199000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4094.947189                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999743                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999743                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          568                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1040                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2341                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1796115775                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1796115775                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    618874540                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       618874540                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    276862898                       # number of WriteReq hits
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index d10bd65d5..20b5204d0 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -120,6 +120,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -136,6 +137,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -158,6 +160,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -174,6 +177,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -183,6 +187,7 @@ eventq_index=0
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -204,6 +209,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -220,6 +226,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -246,7 +253,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
index 1b49765a7..506aa6e28 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
@@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
index f56fe9b31..46359a0c9 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 09:55:43
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:16:43
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 43769191000 because target called exit()
+Exiting @ tick 43690025000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index fc01eaffa..391c7c37b 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.043690                       # Nu
 sim_ticks                                 43690025000                       # Number of ticks simulated
 final_tick                                43690025000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  91247                       # Simulator instruction rate (inst/s)
-host_op_rate                                    91247                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               45127446                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 283120                       # Number of bytes of host memory used
-host_seconds                                   968.15                       # Real time elapsed on the host
+host_inst_rate                                 133116                       # Simulator instruction rate (inst/s)
+host_op_rate                                   133116                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               65834414                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238716                       # Number of bytes of host memory used
+host_seconds                                   663.64                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            454592                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          10138368                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             10592960                       # Number of bytes read from this memory
@@ -331,6 +333,7 @@ system.membus.reqLayer0.occupancy          1218631000                       # La
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1521663500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.5                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                18742723                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          12318363                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           4775680                       # Number of conditional branches incorrect
@@ -442,6 +445,14 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1906.431852                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.930875                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.930875                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2046                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          105                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1090                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          790                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          24821911                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         24821911                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     12250505                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        12250505                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      12250505                       # number of demand (read+write) hits
@@ -550,6 +561,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.826966
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061272                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.054475                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.942712                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32060                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        17071                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13589                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          108                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978394                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          3980332                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3980332                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        79314                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        33055                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         112369                       # number of ReadReq hits
@@ -684,6 +704,13 @@ system.cpu.dcache.tags.warmup_cycle         297515000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4076.382661                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.995211                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.995211                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          922                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3118                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          69984376                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         69984376                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     20180292                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        20180292                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     13574591                       # number of WriteReq hits
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 08705e6b8..f15dfa96f 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -159,6 +159,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -504,6 +506,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -520,6 +523,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -529,6 +533,7 @@ eventq_index=0
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -550,6 +555,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -566,6 +572,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -592,7 +599,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
index 1b49765a7..506aa6e28 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
@@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
index d12ffcc4f..86191115c 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 16 2013 01:34:33
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:24:06
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 24977022500 because target called exit()
+Exiting @ tick 24876941500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 63551bce4..629fb2f13 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.024877                       # Nu
 sim_ticks                                 24876941500                       # Number of ticks simulated
 final_tick                                24876941500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 131928                       # Simulator instruction rate (inst/s)
-host_op_rate                                   131928                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               41235030                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 285168                       # Number of bytes of host memory used
-host_seconds                                   603.30                       # Real time elapsed on the host
+host_inst_rate                                 202143                       # Simulator instruction rate (inst/s)
+host_op_rate                                   202143                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               63181048                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 239772                       # Number of bytes of host memory used
+host_seconds                                   393.74                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            490624                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          10154752                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             10645376                       # Number of bytes read from this memory
@@ -324,6 +326,7 @@ system.membus.reqLayer0.occupancy          1242193000                       # La
 system.membus.reqLayer0.utilization               5.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1539567000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              6.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                16535475                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          10680150                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            413128                       # Number of conditional branches incorrect
@@ -656,6 +659,15 @@ system.cpu.icache.tags.warmup_cycle       20019697250                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1926.124790                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.940491                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.940491                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1531                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          359                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          27896466                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27896466                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     13794941                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        13794941                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      13794941                       # number of demand (read+write) hits
@@ -744,6 +756,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.803864
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064255                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.068608                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.936727                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32069                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          167                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1443                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        18046                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12352                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4           61                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978668                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          4053036                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         4053036                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        86004                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        34262                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         120266                       # number of ReadReq hits
@@ -878,6 +899,13 @@ system.cpu.dcache.tags.warmup_cycle         220306250                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4074.011744                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.994632                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.994632                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1078                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2940                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          71186914                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         71186914                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     20609776                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        20609776                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     13574069                       # number of WriteReq hits
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index c0c8f0dec..16ac17b8d 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,26 @@ icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +108,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +123,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +142,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +152,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
index 1ed796979..506aa6e28 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
@@ -1,7 +1,5 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
index 6c7ff5465..faff61794 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:03:40
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:27:58
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index db9503e0b..35c792878 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.044221                       # Nu
 sim_ticks                                 44221003000                       # Number of ticks simulated
 final_tick                                44221003000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2564036                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2564035                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1283487470                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224620                       # Number of bytes of host memory used
-host_seconds                                    34.45                       # Real time elapsed on the host
+host_inst_rate                                3596409                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3596407                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1800265277                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228820                       # Number of bytes of host memory used
+host_seconds                                    24.56                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         353752292                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         126702647                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            480454939                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@ system.physmem.bw_total::total            12937468537                       # To
 system.membus.throughput                  12937468537                       # Throughput (bytes/s)
 system.membus.data_through_bus              572107835                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index b1fb247dd..927fb8fa4 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -147,6 +165,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +174,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +217,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +232,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +251,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +261,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
index 1b49765a7..506aa6e28 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
@@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
index f89175182..b6a75fdf5 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:04:18
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:28:33
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index bac018361..dd1fcd980 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.133635                       # Nu
 sim_ticks                                133634727000                       # Number of ticks simulated
 final_tick                               133634727000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 775893                       # Simulator instruction rate (inst/s)
-host_op_rate                                   775893                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1173708198                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233104                       # Number of bytes of host memory used
-host_seconds                                   113.86                       # Real time elapsed on the host
+host_inst_rate                                1534458                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1534458                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2321204993                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237688                       # Number of bytes of host memory used
+host_seconds                                    57.57                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            432896                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          10136896                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             10569792                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy          1190991000                       # La
 system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1486377000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -114,6 +117,14 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1871.686406                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.913909                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.913909                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2045                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          191                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1708                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.998535                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         176952584                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        176952584                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     88361638                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        88361638                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      88361638                       # number of demand (read+write) hits
@@ -196,6 +207,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.833083
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.057205                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.047481                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.937769                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32056                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          655                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9976                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        21194                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          117                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978271                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          3900109                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3900109                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        69672                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        33258                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         102930                       # number of ReadReq hits
@@ -330,6 +350,13 @@ system.cpu.dcache.tags.warmup_cycle         936463000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4078.863631                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.995816                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.995816                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          482                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3562                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          69984374                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         69984374                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     20215872                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        20215872                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     14469799                       # number of WriteReq hits
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 9b769867b..3a6f7de14 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -159,6 +159,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,7 +632,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/dist/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
index 946783e23..51d96dffd 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:08:44
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:17:11
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 26765004500 because target called exit()
+Exiting @ tick 26810051000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index df6074257..044953ad0 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.026810                       # Nu
 sim_ticks                                 26810051000                       # Number of ticks simulated
 final_tick                                26810051000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  86453                       # Simulator instruction rate (inst/s)
-host_op_rate                                   122688                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               32687774                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303000                       # Number of bytes of host memory used
-host_seconds                                   820.19                       # Real time elapsed on the host
+host_inst_rate                                 140336                       # Simulator instruction rate (inst/s)
+host_op_rate                                   199155                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               53060871                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257660                       # Number of bytes of host memory used
+host_seconds                                   505.27                       # Real time elapsed on the host
 sim_insts                                    70907629                       # Number of instructions simulated
 sim_ops                                     100626876                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            299136                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7943232                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              8242368                       # Number of bytes read from this memory
@@ -333,6 +335,7 @@ system.membus.reqLayer0.occupancy           934752500                       # La
 system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1203686693                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              4.5                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                16646392                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          12773976                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            607235                       # Number of conditional branches incorrect
@@ -678,6 +681,14 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1808.840382                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.883223                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.883223                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2039                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1260                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          677                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.995605                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          23425177                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         23425177                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     11662047                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        11662047                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      11662047                       # number of demand (read+write) hits
@@ -766,6 +777,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.813945
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.041899                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.056290                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.912134                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31104                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1849                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        20230                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         8498                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          395                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949219                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          2814320                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         2814320                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        25996                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        33476                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          59472                       # number of ReadReq hits
@@ -929,6 +949,13 @@ system.cpu.dcache.tags.warmup_cycle         363282250                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4068.859504                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.993374                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.993374                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1767                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2268                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          92301717                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         92301717                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     26063246                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        26063246                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     18266759                       # number of WriteReq hits
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 6172e5c1a..b4899830a 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@ icache_port=system.membus.slave[1]
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,7 +141,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -143,11 +156,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
index cdf0f47ec..fd88c13a1 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:45:30
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:25:48
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 9f4bab8c0..130b6bb56 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.053932                       # Nu
 sim_ticks                                 53932157000                       # Number of ticks simulated
 final_tick                                53932157000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2080365                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2952231                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1582195312                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241268                       # Number of bytes of host memory used
-host_seconds                                    34.09                       # Real time elapsed on the host
+host_inst_rate                                1940189                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2753308                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1475586020                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 245844                       # Number of bytes of host memory used
+host_seconds                                    36.55                       # Real time elapsed on the host
 sim_insts                                    70913181                       # Number of instructions simulated
 sim_ops                                     100632428                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         312580272                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         106573345                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            419153617                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@ system.physmem.bw_total::total             9230371187                       # To
 system.membus.throughput                   9230371187                       # Throughput (bytes/s)
 system.membus.data_through_bus              497813828                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index 5e9534bc1..8802837e9 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,7 +250,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -239,11 +265,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
index 67309511e..89bb0e0aa 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:31:35
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:26:35
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 178d6c7df..7d6b41b45 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.132689                       # Nu
 sim_ticks                                132689045000                       # Number of ticks simulated
 final_tick                               132689045000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 525201                       # Simulator instruction rate (inst/s)
-host_op_rate                                   744748                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              990262559                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 247408                       # Number of bytes of host memory used
-host_seconds                                   133.99                       # Real time elapsed on the host
+host_inst_rate                                1019812                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1446120                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1922848599                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254584                       # Number of bytes of host memory used
+host_seconds                                    69.01                       # Real time elapsed on the host
 sim_insts                                    70373628                       # Number of instructions simulated
 sim_ops                                      99791654                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            255488                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7924480                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              8179968                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy           882993000                       # La
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1150308000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -124,6 +127,14 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1736.497265                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.847899                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.847899                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2018                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          184                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1755                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.985352                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         156309046                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        156309046                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     78126161                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        78126161                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      78126161                       # number of demand (read+write) hits
@@ -206,6 +217,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.846737
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035218                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.044809                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.926764                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31095                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          428                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        10156                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        19788                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          616                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.948944                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          2689980                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         2689980                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        14916                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        31426                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          46342                       # number of ReadReq hits
@@ -340,6 +360,13 @@ system.cpu.dcache.tags.warmup_cycle        1072595000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4076.954355                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.995350                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.995350                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          443                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3604                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          94204142                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         94204142                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     27087367                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        27087367                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     19742869                       # number of WriteReq hits
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 0f57053cc..abfb7932e 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,25 @@ icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +107,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+eventq_index=0
+executable=/dist/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +122,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +141,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +151,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
index 401e0da87..f7abb9a35 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
@@ -1,4 +1,3 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall time(4026528248, 4026527848, ...)
 warn: ignoring syscall time(1375098, 4026527400, ...)
@@ -561,4 +560,3 @@ warn: ignoring syscall time(4026526436, 4026525968, ...)
 warn: ignoring syscall time(7004192, 4026526056, ...)
 warn: ignoring syscall time(4, 4026527512, ...)
 warn: ignoring syscall time(0, 4026525760, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
index c44643a8d..9c35a9a4f 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:07:56
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:46:20
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index 0c3e0f3fc..f2f248de4 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.068149                       # Nu
 sim_ticks                                 68148672000                       # Number of ticks simulated
 final_tick                                68148672000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2813738                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2850169                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1426739476                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233072                       # Number of bytes of host memory used
-host_seconds                                    47.77                       # Real time elapsed on the host
+host_inst_rate                                3132375                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3172933                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1588309038                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237324                       # Number of bytes of host memory used
+host_seconds                                    42.91                       # Real time elapsed on the host
 sim_insts                                   134398962                       # Number of instructions simulated
 sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         538214280                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         147559360                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            685773640                       # Number of bytes read from this memory
@@ -38,6 +40,7 @@ system.physmem.bw_total::total            11381829862                       # To
 system.membus.throughput                  11383698247                       # Throughput (bytes/s)
 system.membus.data_through_bus              775783918                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 system.cpu.numCycles                        136297345                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index e7e0ce2f8..937ce3e41 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -147,6 +164,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +173,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +188,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +206,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +216,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+eventq_index=0
+executable=/dist/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +231,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +250,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +260,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
index bb51748c6..f7abb9a35 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
@@ -560,4 +560,3 @@ warn: ignoring syscall time(4026526436, 4026525968, ...)
 warn: ignoring syscall time(7004192, 4026526056, ...)
 warn: ignoring syscall time(4, 4026527512, ...)
 warn: ignoring syscall time(0, 4026525760, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
index 7747f2ffd..2ff984591 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:10:51
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:47:13
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index b5bc877a9..7fe81f58a 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.202242                       # Nu
 sim_ticks                                202242260000                       # Number of ticks simulated
 final_tick                               202242260000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 788005                       # Simulator instruction rate (inst/s)
-host_op_rate                                   798208                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1185781953                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240044                       # Number of bytes of host memory used
-host_seconds                                   170.56                       # Real time elapsed on the host
+host_inst_rate                                1441010                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1459668                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2168416558                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246160                       # Number of bytes of host memory used
+host_seconds                                    93.27                       # Real time elapsed on the host
 sim_insts                                   134398962                       # Number of instructions simulated
 sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            591488                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7826624                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              8418112                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy           877345000                       # La
 system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1183797000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 system.cpu.numCycles                        404484520                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -82,6 +85,15 @@ system.cpu.icache.tags.warmup_cycle      143972294000                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  2004.815325                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.978914                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.978914                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           74                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          456                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1427                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         269294166                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        269294166                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    134366547                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       134366547                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     134366547                       # number of demand (read+write) hits
@@ -164,6 +176,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.800951
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.103331                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.037209                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.941490                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        30994                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          533                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12212                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17536                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          585                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.945862                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          3928089                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3928089                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst       177782                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        24464                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         202246                       # number of ReadReq hits
@@ -298,6 +319,13 @@ system.cpu.dcache.tags.warmup_cycle         769040000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4087.648350                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997961                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997961                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          529                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3530                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         116373718                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        116373718                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     37185801                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        37185801                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     20759140                       # number of WriteReq hits
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
index cd7da392b..317ef3f76 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
@@ -120,6 +120,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -136,6 +137,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -158,6 +160,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -174,6 +177,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -183,6 +187,7 @@ eventq_index=0
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -204,6 +209,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -220,6 +226,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -246,7 +253,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
index 1b49765a7..506aa6e28 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
@@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
index 037bfdea9..45898c91d 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:05:17
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:29:41
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -23,4 +23,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 1017016979500 because target called exit()
+Exiting @ tick 1009838214500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index 864d4a591..01fe4f841 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  1.009838                       # Nu
 sim_ticks                                1009838214500                       # Number of ticks simulated
 final_tick                               1009838214500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  87394                       # Simulator instruction rate (inst/s)
-host_op_rate                                    87394                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               48496748                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275936                       # Number of bytes of host memory used
-host_seconds                                 20822.81                       # Real time elapsed on the host
+host_inst_rate                                 128161                       # Simulator instruction rate (inst/s)
+host_op_rate                                   128161                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               71119760                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230508                       # Number of bytes of host memory used
+host_seconds                                 14199.12                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             54976                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         125365056                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            125420032                       # Number of bytes read from this memory
@@ -325,6 +327,7 @@ system.membus.reqLayer0.occupancy         11785228500                       # La
 system.membus.reqLayer0.utilization               1.2                       # Layer utilization (%)
 system.membus.respLayer1.occupancy        18364778000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.8                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups               326538257                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         252572868                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect         138234365                       # Number of conditional branches incorrect
@@ -436,6 +439,12 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   668.332859                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.326334                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.326334                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          858                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          785                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.418945                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         463858599                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        463858599                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    231927731                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       231927731                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     231927731                       # number of demand (read+write) hits
@@ -544,6 +553,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.455687
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001058                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.486850                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.943594                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29793                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          613                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          725                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12815                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15482                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909210                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        106291061                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       106291061                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.data      6044291                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6044291                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3693280                       # number of Writeback hits
@@ -675,6 +693,14 @@ system.cpu.dcache.tags.warmup_cycle       12709353000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4082.357931                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.996669                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.996669                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          590                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2876                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          593                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           37                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1219759777                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1219759777                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    437268777                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       437268777                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    156014425                       # number of WriteReq hits
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 3e178e75c..20db05a32 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -159,6 +159,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -504,6 +506,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -520,6 +523,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -529,6 +533,7 @@ eventq_index=0
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -550,6 +555,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -566,6 +572,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -592,7 +599,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
index 1b49765a7..506aa6e28 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
@@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 3d7fe8a25..b7f8b903e 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 15 2013 19:07:40
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:30:51
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -25,4 +23,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 694171131000 because target called exit()
+Exiting @ tick 685386545000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 29e4de429..09d12ecba 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.685387                       # Nu
 sim_ticks                                685386545000                       # Number of ticks simulated
 final_tick                               685386545000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 111182                       # Simulator instruction rate (inst/s)
-host_op_rate                                   111182                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               43894428                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 276060                       # Number of bytes of host memory used
-host_seconds                                 15614.43                       # Real time elapsed on the host
+host_inst_rate                                 166100                       # Simulator instruction rate (inst/s)
+host_op_rate                                   166100                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               65575812                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231660                       # Number of bytes of host memory used
+host_seconds                                 10451.82                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             61760                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         125792064                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            125853824                       # Number of bytes read from this memory
@@ -326,6 +328,7 @@ system.membus.reqLayer0.occupancy         11873404000                       # La
 system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
 system.membus.respLayer1.occupancy        18493738500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              2.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups               381642976                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         296606399                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          16082111                       # Number of conditional branches incorrect
@@ -657,6 +660,13 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   773.100738                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.377491                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.377491                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          964                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          907                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.470703                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         782110757                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        782110757                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    391053395                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       391053395                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     391053395                       # number of demand (read+write) hits
@@ -745,6 +755,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.445145
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000819                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.513002                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.958966                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29778                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          978                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          594                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17297                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10763                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908752                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        107098856                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       107098856                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.data      6106330                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6106330                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3725230                       # number of Writeback hits
@@ -876,6 +895,14 @@ system.cpu.dcache.tags.warmup_cycle        5178034250                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4087.561673                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997940                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997940                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          690                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2994                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          408                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1430860164                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1430860164                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    538716411                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       538716411                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    155539725                       # number of WriteReq hits
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index 86a7050c2..6cbd45db6 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,26 @@ icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +108,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +123,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +142,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +152,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
index 1ed796979..506aa6e28 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
@@ -1,7 +1,5 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
index 33b8f7ad8..1dfd46cbe 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:09:10
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:36:30
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index 87abf8a8a..8ad24bba9 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.913189                       # Nu
 sim_ticks                                913189263000                       # Number of ticks simulated
 final_tick                               913189263000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4050769                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4050768                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2032728095                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217548                       # Number of bytes of host memory used
-host_seconds                                   449.24                       # Real time elapsed on the host
+host_inst_rate                                3833053                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3833053                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1923475514                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220744                       # Number of bytes of host memory used
+host_seconds                                   474.76                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        7305514036                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        1974795935                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           9280309971                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@ system.physmem.bw_total::total            11068994882                       # To
 system.membus.throughput                  11068994882                       # Throughput (bytes/s)
 system.membus.data_through_bus            10108087278                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 482b126d1..2cb068091 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -147,6 +165,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +174,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +217,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +232,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +251,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +261,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
index 1b49765a7..506aa6e28 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
@@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 154161af5..43eef16e9 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:14:34
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:44:35
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 27c712d4a..894d37cbc 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  2.623386                       # Nu
 sim_ticks                                2623386226000                       # Number of ticks simulated
 final_tick                               2623386226000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1731328                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1731328                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2495874089                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225024                       # Number of bytes of host memory used
-host_seconds                                  1051.09                       # Real time elapsed on the host
+host_inst_rate                                1625838                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1625838                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2343799751                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229480                       # Number of bytes of host memory used
+host_seconds                                  1119.29                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             51328                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         125367104                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            125418432                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy         11122356000                       # La
 system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
 system.membus.respLayer1.occupancy        17636967000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -114,6 +117,12 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   612.458646                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.299052                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.299052                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          801                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          730                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.391113                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        3652757822                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       3652757822                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst   1826377708                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1826377708                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1826377708                       # number of demand (read+write) hits
@@ -196,6 +205,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.464535
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001192                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.466135                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.931862                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29792                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1059                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1254                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27303                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909180                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        106294313                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       106294313                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.data      6044854                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6044854                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3693497                       # number of Writeback hits
@@ -327,6 +345,15 @@ system.cpu.dcache.tags.warmup_cycle       40977439000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4079.262869                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.995914                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.995914                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1238                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2584                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          200                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1219760064                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1219760064                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    437373249                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       437373249                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    158839182                       # number of WriteReq hits
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index d4b45072d..c32ff375e 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -159,6 +159,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,7 +632,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
index b4d96e4ea..5d8946ede 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index 7f1aa9216..aa09d1777 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:37:44
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:27:54
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -24,4 +24,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 541686426500 because target called exit()
+Exiting @ tick 533797009000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 19d70b574..5e5db11e7 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.533797                       # Nu
 sim_ticks                                533797009000                       # Number of ticks simulated
 final_tick                               533797009000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 102910                       # Simulator instruction rate (inst/s)
-host_op_rate                                   114803                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               35565366                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 295220                       # Number of bytes of host memory used
-host_seconds                                 15008.90                       # Real time elapsed on the host
+host_inst_rate                                 163502                       # Simulator instruction rate (inst/s)
+host_op_rate                                   182399                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               56505895                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249880                       # Number of bytes of host memory used
+host_seconds                                  9446.75                       # Real time elapsed on the host
 sim_insts                                  1544563023                       # Number of instructions simulated
 sim_ops                                    1723073835                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             47680                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         143743296                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            143790976                       # Number of bytes read from this memory
@@ -327,6 +329,7 @@ system.membus.reqLayer0.occupancy         12926153000                       # La
 system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
 system.membus.respLayer1.occupancy        21085487000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              4.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups               303451211                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         249690817                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          15200865                       # Number of conditional branches incorrect
@@ -668,6 +671,13 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   628.438821                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.306855                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.306855                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          754                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          726                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.368164                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         579143830                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        579143830                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    289570320                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       289570320                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     289570320                       # number of demand (read+write) hits
@@ -756,6 +766,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.436471
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000618                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.525223                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.962312                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29773                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1896                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        23750                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3957                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908600                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        111203780                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       111203780                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           28                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      6288761                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6288789                       # number of ReadReq hits
@@ -899,6 +918,14 @@ system.cpu.dcache.tags.warmup_cycle        3547188250                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4088.041920                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.998057                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.998057                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          642                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2397                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1056                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1355914350                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1355914350                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    489062653                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       489062653                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    166956698                       # number of WriteReq hits
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index 4c52e043e..1a911e7c2 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@ icache_port=system.membus.slave[1]
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,7 +141,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -143,11 +156,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
index 836ec0832..922328096 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:33:02
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:35:09
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index c05db510c..de1eec5b4 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.861538                       # Nu
 sim_ticks                                861538200000                       # Number of ticks simulated
 final_tick                               861538200000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2812355                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3137389                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1568696760                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234512                       # Number of bytes of host memory used
-host_seconds                                   549.21                       # Real time elapsed on the host
+host_inst_rate                                2414882                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2693979                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1346991470                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238968                       # Number of bytes of host memory used
+host_seconds                                   639.60                       # Real time elapsed on the host
 sim_insts                                  1544563041                       # Number of instructions simulated
 sim_ops                                    1723073853                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        6178262356                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        1581387671                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           7759650027                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@ system.physmem.bw_total::total             9731209155                       # To
 system.membus.throughput                   9731209155                       # Throughput (bytes/s)
 system.membus.data_through_bus             8383808419                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 0b3714a01..05924440e 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,7 +250,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -239,11 +265,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
index 8e102e919..684ae1ce5 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:46:27
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:38:44
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 0ee21876c..3ce47f2c9 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  2.391205                       # Nu
 sim_ticks                                2391205115000                       # Number of ticks simulated
 final_tick                               2391205115000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 594937                       # Simulator instruction rate (inst/s)
-host_op_rate                                   663956                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              924522029                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240640                       # Number of bytes of host memory used
-host_seconds                                  2586.42                       # Real time elapsed on the host
+host_inst_rate                                1202285                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1341761                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1868329144                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247832                       # Number of bytes of host memory used
+host_seconds                                  1279.86                       # Real time elapsed on the host
 sim_insts                                  1538759601                       # Number of instructions simulated
 sim_ops                                    1717270334                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             39424                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         125322112                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            125361536                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy         11113556000                       # La
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
 system.membus.respLayer1.occupancy        17628966000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -124,6 +127,13 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   514.976015                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.251453                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.251453                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          631                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          606                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.308105                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        3089131818                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       3089131818                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst   1544564952                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1544564952                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1544564952                       # number of demand (read+write) hits
@@ -206,6 +216,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.477554
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000737                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.467360                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.945651                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29768                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1082                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1693                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26880                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908447                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        106351328                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       106351328                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           22                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      6048805                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6048827                       # number of ReadReq hits
@@ -340,6 +359,15 @@ system.cpu.dcache.tags.warmup_cycle       25914401000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4083.522356                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.996954                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.996954                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1214                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2578                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1319055826                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1319055826                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    475158039                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       475158039                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    170696898                       # number of WriteReq hits
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 593d636da..40d9825c1 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -76,16 +81,19 @@ icache_port=system.membus.slave[1]
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
@@ -93,6 +101,7 @@ port=system.membus.slave[4]
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -103,22 +112,26 @@ pio=system.membus.master[1]
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -128,7 +141,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -142,11 +156,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -159,6 +175,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -168,5 +185,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
index 5a2f2668d..ff491d90e 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:38:48
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 21:14:55
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 256e15dc9..5fca1ed49 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  2.846007                       # Nu
 sim_ticks                                2846007227500                       # Number of ticks simulated
 final_tick                               2846007227500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1357896                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2115724                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1284732870                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240864                       # Number of bytes of host memory used
-host_seconds                                  2215.25                       # Real time elapsed on the host
+host_inst_rate                                1743046                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2715824                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1649131867                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 242928                       # Number of bytes of host memory used
+host_seconds                                  1725.76                       # Real time elapsed on the host
 sim_insts                                  3008081022                       # Number of instructions simulated
 sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst       32105863056                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        5023868345                       # Number of bytes read from this memory
 system.physmem.bytes_read::total          37129731401                       # Number of bytes read from this memory
@@ -36,6 +38,8 @@ system.physmem.bw_total::total            13588998587                       # To
 system.membus.throughput                  13588998587                       # Throughput (bytes/s)
 system.membus.data_through_bus            38674388193                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
 system.cpu.numCycles                       5692014456                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index 8de21ec08..5c76444e5 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -69,6 +74,7 @@ icache_port=system.cpu.icache.cpu_side
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dcache]
 type=BaseCache
@@ -76,6 +82,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -84,6 +91,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -98,18 +106,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
@@ -120,6 +132,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -128,6 +141,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -142,12 +156,15 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -158,16 +175,19 @@ pio=system.membus.master[1]
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
@@ -178,6 +198,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -186,6 +207,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -200,12 +222,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -215,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -224,7 +250,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -238,11 +265,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -255,6 +284,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -264,5 +294,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index 2a7659f1c..d2167f766 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:55:52
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 21:25:13
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index f740c02c8..49729ff93 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  5.882581                       # Nu
 sim_ticks                                5882580526000                       # Number of ticks simulated
 final_tick                               5882580526000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 876676                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1365940                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1714420225                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249312                       # Number of bytes of host memory used
-host_seconds                                  3431.24                       # Real time elapsed on the host
+host_inst_rate                                 833754                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1299064                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1630482633                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251632                       # Number of bytes of host memory used
+host_seconds                                  3607.88                       # Real time elapsed on the host
 sim_insts                                  3008081022                       # Number of instructions simulated
 sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             43200                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         125326976                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            125370176                       # Number of bytes read from this memory
@@ -52,6 +54,8 @@ system.membus.reqLayer0.occupancy         11124698000                       # La
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
 system.membus.respLayer1.occupancy        17630181000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
 system.cpu.numCycles                      11765161052                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -86,6 +90,12 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   555.705054                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.271340                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.271340                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          665                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          632                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.324707                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        8026466441                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       8026466441                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst   4013232208                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      4013232208                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    4013232208                       # number of demand (read+write) hits
@@ -168,6 +178,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.469873
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000783                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.479548                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.950203                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29783                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          996                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          743                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27921                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908905                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        106336271                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       106336271                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.data      6045911                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6045911                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3697956                       # number of Writeback hits
@@ -299,6 +318,15 @@ system.cpu.dcache.tags.warmup_cycle       58853922000                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  4084.587030                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997214                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997214                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          926                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2744                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          320                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        3364538845                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       3364538845                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data   1231961896                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total      1231961896                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    436638511                       # number of WriteReq hits
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
index 8a347565f..1a6e862fe 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
@@ -120,6 +120,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -136,6 +137,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -158,6 +160,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -174,6 +177,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -183,6 +187,7 @@ eventq_index=0
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -204,6 +209,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -220,6 +226,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -246,7 +253,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
index 1b49765a7..506aa6e28 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
@@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
index 27c876af5..66d60adf3 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:18:38
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 19:03:25
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 41671895000 because target called exit()
+122 123 124 Exiting @ tick 41680207000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index 5f89f07e5..3f6e9d455 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.041680                       # Nu
 sim_ticks                                 41680207000                       # Number of ticks simulated
 final_tick                                41680207000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  93645                       # Simulator instruction rate (inst/s)
-host_op_rate                                    93645                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               42470141                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 279708                       # Number of bytes of host memory used
-host_seconds                                   981.40                       # Real time elapsed on the host
+host_inst_rate                                 131207                       # Simulator instruction rate (inst/s)
+host_op_rate                                   131207                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59505524                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 234284                       # Number of bytes of host memory used
+host_seconds                                   700.44                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            178816                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            137216                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               316032                       # Number of bytes read from this memory
@@ -243,6 +245,7 @@ system.membus.reqLayer0.occupancy             5775000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           45973500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                13412627                       # Number of BP lookups
 system.cpu.branchPred.condPredicted           9650146                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           4269214                       # Number of conditional branches incorrect
@@ -354,6 +357,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1492.182806                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.728605                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.728605                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1885                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          613                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          136                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          959                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.920410                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          19923420                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         19923420                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst      9945551                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total         9945551                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst       9945551                       # number of demand (read+write) hits
@@ -462,6 +474,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.000545
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.055565                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.010711                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.066821                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3282                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          129                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          700                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          168                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2213                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.100159                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            99830                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           99830                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         6726                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           53                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           6779                       # number of ReadReq hits
@@ -594,6 +615,15 @@ system.cpu.dcache.tags.warmup_cycle                 0                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  1441.367780                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.351896                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.351896                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2066                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           58                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          211                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          403                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1372                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.504395                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          52996825                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         52996825                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     19995621                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        19995621                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      6492829                       # number of WriteReq hits
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 201e62f46..78509c3e8 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -159,6 +159,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -504,6 +506,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -520,6 +523,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -529,6 +533,7 @@ eventq_index=0
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -550,6 +555,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -566,6 +572,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -592,7 +599,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
index 1b49765a7..506aa6e28 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
@@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
index 2fe61da2d..c12c73ccb 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 16 2013 01:34:33
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 19:15:16
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 23492267500 because target called exit()
+122 123 124 Exiting @ tick 23461709500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 445692444..b0acaf58e 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.023462                       # Nu
 sim_ticks                                 23461709500                       # Number of ticks simulated
 final_tick                                23461709500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 127245                       # Simulator instruction rate (inst/s)
-host_op_rate                                   127245                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               35464472                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 280732                       # Number of bytes of host memory used
-host_seconds                                   661.56                       # Real time elapsed on the host
+host_inst_rate                                 186682                       # Simulator instruction rate (inst/s)
+host_op_rate                                   186682                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               52030153                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235304                       # Number of bytes of host memory used
+host_seconds                                   450.93                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            195968                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            138624                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               334592                       # Number of bytes read from this memory
@@ -244,6 +246,7 @@ system.membus.reqLayer0.occupancy             6831000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           49012250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                14847721                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          10774921                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            922205                       # Number of conditional branches incorrect
@@ -576,6 +579,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1596.482984                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.779533                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.779533                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1934                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          184                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          766                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          924                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.944336                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          29479830                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         29479830                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     14719872                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        14719872                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      14719872                       # number of demand (read+write) hits
@@ -664,6 +676,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.000540
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061354                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.011641                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.073535                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3590                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          910                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2431                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109558                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           116249                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          116249                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         8448                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           55                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           8503                       # number of ReadReq hits
@@ -796,6 +817,14 @@ system.cpu.dcache.tags.warmup_cycle                 0                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  1459.152638                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.356238                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.356238                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2088                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          542                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1390                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.509766                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          56179001                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         56179001                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     21586035                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        21586035                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      6492869                       # number of WriteReq hits
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 04249e1da..b06f5d885 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,26 @@ icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +108,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +123,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +142,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +152,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
index 1ed796979..506aa6e28 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
@@ -1,7 +1,5 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
index 508377532..53155afb5 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:32:22
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 19:22:57
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index 31612b0d4..69d43d9de 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.045952                       # Nu
 sim_ticks                                 45951567500                       # Number of ticks simulated
 final_tick                                45951567500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3944537                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3944535                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1972268010                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220188                       # Number of bytes of host memory used
-host_seconds                                    23.30                       # Real time elapsed on the host
+host_inst_rate                                2604589                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2604587                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1302294342                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224388                       # Number of bytes of host memory used
+host_seconds                                    35.29                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         367612356                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         108337521                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            475949877                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@ system.physmem.bw_total::total            11030545389                       # To
 system.membus.throughput                  11030545389                       # Throughput (bytes/s)
 system.membus.data_through_bus              506870851                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 2ef8f2342..3fa897910 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -147,6 +165,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +174,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +217,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +232,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +251,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +261,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
index 1b49765a7..506aa6e28 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
@@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
index b809995e1..078852d80 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:32:58
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 19:23:43
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index be0605d18..d8a9ee89f 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.118729                       # Nu
 sim_ticks                                118729316000                       # Number of ticks simulated
 final_tick                               118729316000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2022504                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2022504                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2612866318                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228676                       # Number of bytes of host memory used
-host_seconds                                    45.44                       # Real time elapsed on the host
+host_inst_rate                                1382014                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1382013                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1785419086                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 233256                       # Number of bytes of host memory used
+host_seconds                                    66.50                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            167744                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            137216                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               304960                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy             4765000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           42885000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -106,6 +109,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1418.052773                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.692409                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.692409                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1829                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          585                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          953                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.893066                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         183814690                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        183814690                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     91894580                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        91894580                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      91894580                       # number of demand (read+write) hits
@@ -188,6 +200,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.000543
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.052033                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.010720                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.063296                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3109                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          221                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          703                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2096                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.094879                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            91577                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           91577                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         5889                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           53                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           5942                       # number of ReadReq hits
@@ -320,6 +341,15 @@ system.cpu.dcache.tags.warmup_cycle                 0                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  1442.043392                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.352061                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.352061                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2066                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          173                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          487                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1372                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.504395                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          52996825                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         52996825                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     19995723                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        19995723                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      6499355                       # number of WriteReq hits
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 90382fb26..69c7d8edb 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -159,6 +159,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,7 +632,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/dist/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index 5ce7704c2..6ec033969 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:15:41
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:45:59
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -21,4 +23,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 74201024500 because target called exit()
+122 123 124 Exiting @ tick 74219948500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index ac21abc99..3723ab1c1 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.074220                       # Nu
 sim_ticks                                 74219948500                       # Number of ticks simulated
 final_tick                                74219948500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  84730                       # Simulator instruction rate (inst/s)
-host_op_rate                                    92772                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               36497737                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 298520                       # Number of bytes of host memory used
-host_seconds                                  2033.55                       # Real time elapsed on the host
+host_inst_rate                                 133200                       # Simulator instruction rate (inst/s)
+host_op_rate                                   145842                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               57376166                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253176                       # Number of bytes of host memory used
+host_seconds                                  1293.57                       # Real time elapsed on the host
 sim_insts                                   172303021                       # Number of instructions simulated
 sim_ops                                     188656503                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            131072                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            111680                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               242752                       # Number of bytes read from this memory
@@ -237,6 +239,7 @@ system.membus.reqLayer0.occupancy             4682500                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           35532750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                94784274                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          74784006                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           6281562                       # Number of conditional branches incorrect
@@ -581,6 +584,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1347.740549                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.658076                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.658076                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1731                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          544                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           27                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1037                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.845215                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          73705913                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         73705913                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     36845557                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        36845557                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      36845557                       # number of demand (read+write) hits
@@ -669,6 +681,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.000152
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.043505                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.016384                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.060042                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2732                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          604                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3           28                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1970                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.083374                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            51779                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           51779                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         2073                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           88                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           2161                       # number of ReadReq hits
@@ -810,6 +831,15 @@ system.cpu.dcache.tags.warmup_cycle                 0                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  1406.103135                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.343287                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.343287                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1795                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          353                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1378                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.438232                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          93593418                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         93593418                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     34384711                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        34384711                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     12356564                       # number of WriteReq hits
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 46e3b79d7..0b27d47af 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@ icache_port=system.membus.slave[1]
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,7 +141,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -143,11 +156,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
index debc9398c..3a7a72087 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:16:29
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 23 2014 00:00:14
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 24cdef337..c33d29231 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.103107                       # Nu
 sim_ticks                                103106766000                       # Number of ticks simulated
 final_tick                               103106766000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2813934                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3080985                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1683727447                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236772                       # Number of bytes of host memory used
-host_seconds                                    61.24                       # Real time elapsed on the host
+host_inst_rate                                2018881                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2210479                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1208004529                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 241364                       # Number of bytes of host memory used
+host_seconds                                    85.35                       # Real time elapsed on the host
 sim_insts                                   172317409                       # Number of instructions simulated
 sim_ops                                     188670891                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         759440204                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         110533661                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            869973865                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@ system.physmem.bw_total::total             8876496088                       # To
 system.membus.throughput                   8876496088                       # Throughput (bytes/s)
 system.membus.data_through_bus              915226805                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
index beab37699..a68b7deda 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,7 +250,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -239,11 +265,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
index 559353937..50f61b81e 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:33:12
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 23 2014 00:01:50
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 3a3e9e512..daccb0e4d 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.232072                       # Nu
 sim_ticks                                232072304000                       # Number of ticks simulated
 final_tick                               232072304000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 705973                       # Simulator instruction rate (inst/s)
-host_op_rate                                   773116                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              953412259                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242928                       # Number of bytes of host memory used
-host_seconds                                   243.41                       # Real time elapsed on the host
+host_inst_rate                                1248624                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1367377                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1686259354                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250108                       # Number of bytes of host memory used
+host_seconds                                   137.63                       # Real time elapsed on the host
 sim_insts                                   171842483                       # Number of instructions simulated
 sim_ops                                     188185920                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            110656                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            110336                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               220992                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy             3453000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           31077000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -116,6 +119,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1147.986161                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.560540                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.560540                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1545                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          288                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          270                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          942                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.754395                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         379723155                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        379723155                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    189857001                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       189857001                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     189857001                       # number of demand (read+write) hits
@@ -198,6 +210,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.000093
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035676                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.015368                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.051137                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2369                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          320                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          322                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1679                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.072296                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            42317                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           42317                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         1322                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           57                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           1379                       # number of ReadReq hits
@@ -330,6 +351,15 @@ system.cpu.dcache.tags.warmup_cycle                 0                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  1363.611259                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.332913                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.332913                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1749                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           14                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          302                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1345                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.427002                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          84020083                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         84020083                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     29599357                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        29599357                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     12363187                       # number of WriteReq hits
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 450711784..ead3fce75 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,25 @@ icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +107,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/sparc/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +122,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +141,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +151,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
index 7edd901b2..1a4f96712 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
@@ -1,3 +1 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
index 1f1c88e44..522507bd6 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:10:38
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:48:57
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
 Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav
 Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index 806cadbfa..b414e1534 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.096723                       # Nu
 sim_ticks                                 96722945000                       # Number of ticks simulated
 final_tick                                96722945000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3763101                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3763105                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1881563141                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229516                       # Number of bytes of host memory used
-host_seconds                                    51.41                       # Real time elapsed on the host
+host_inst_rate                                2588672                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2588674                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1294344494                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 233760                       # Number of bytes of host memory used
+host_seconds                                    74.73                       # Real time elapsed on the host
 sim_insts                                   193444518                       # Number of instructions simulated
 sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         773782140                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         223463413                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            997245553                       # Number of bytes read from this memory
@@ -38,6 +40,7 @@ system.physmem.bw_total::total            11055401229                       # To
 system.membus.throughput                  11057254439                       # Throughput (bytes/s)
 system.membus.data_through_bus             1069490213                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  401                       # Number of system calls
 system.cpu.numCycles                        193445891                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
index bac902cb5..5f60b5786 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -147,6 +164,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +173,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +188,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +206,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +216,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/sparc/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +231,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +250,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +260,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
index 139366506..cbae3bd7a 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:08:55
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:50:23
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
 Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
 Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index 471075dde..4c0f0b47e 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.270563                       # Nu
 sim_ticks                                270563082000                       # Number of ticks simulated
 final_tick                               270563082000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 872463                       # Simulator instruction rate (inst/s)
-host_op_rate                                   872464                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1220278409                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236504                       # Number of bytes of host memory used
-host_seconds                                   221.72                       # Real time elapsed on the host
+host_inst_rate                                1313314                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1313315                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1836878526                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 242660                       # Number of bytes of host memory used
+host_seconds                                   147.30                       # Real time elapsed on the host
 sim_insts                                   193444518                       # Number of instructions simulated
 sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            230208                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            100864                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               331072                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy             5173000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           46557000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  401                       # Number of system calls
 system.cpu.numCycles                        541126164                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -74,6 +77,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1591.579171                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.777138                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.777138                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1926                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           50                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          624                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          514                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          687                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.940430                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         386903360                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        386903360                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    193433248                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       193433248                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     193433248                       # number of demand (read+write) hits
@@ -156,6 +168,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.000000
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.069436                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.012300                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.081736                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4097                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           40                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          700                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          625                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2688                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.125031                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           116103                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          116103                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         8691                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           8691                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks            2                       # number of Writeback hits
@@ -283,6 +304,15 @@ system.cpu.dcache.tags.warmup_cycle                 0                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  1237.203941                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.302052                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.302052                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1574                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0            5                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          271                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1237                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.384277                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         153469402                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        153469402                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     57734570                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        57734570                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     18975362                       # number of WriteReq hits
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index 210f89c36..e8d7fb666 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -165,6 +165,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -181,6 +182,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -520,6 +522,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -536,6 +539,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,7 +632,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index 607420641..1e66bd991 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:39:37
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 21:43:52
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -22,4 +24,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 144337151000 because target called exit()
+122 123 124 Exiting @ tick 144463317000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 3f8722e89..1427887bb 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.144463                       # Nu
 sim_ticks                                144463317000                       # Number of ticks simulated
 final_tick                               144463317000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  55445                       # Simulator instruction rate (inst/s)
-host_op_rate                                    92931                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               60647702                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 328672                       # Number of bytes of host memory used
-host_seconds                                  2382.01                       # Real time elapsed on the host
+host_inst_rate                                  81167                       # Simulator instruction rate (inst/s)
+host_op_rate                                   136043                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               88782348                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 282908                       # Number of bytes of host memory used
+host_seconds                                  1627.16                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            217088                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            125568                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               342656                       # Number of bytes read from this memory
@@ -251,6 +253,7 @@ system.membus.reqLayer0.occupancy             6950000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           50662837                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                18648233                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          18648233                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           1490176                       # Number of conditional branches incorrect
@@ -260,6 +263,7 @@ system.cpu.branchPred.BTBCorrect                    0                       # Nu
 system.cpu.branchPred.BTBHitPct             94.591126                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 1320367                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect              22841                       # Number of incorrect RAS predictions.
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
 system.cpu.numCycles                        289221873                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -552,6 +556,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1619.938452                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.790986                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.790986                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1967                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          185                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          767                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          122                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          797                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.960449                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          44713203                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         44713203                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     22344300                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        22344300                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      22344300                       # number of demand (read+write) hits
@@ -640,6 +653,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.000053
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.068064                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.009517                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.077634                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3826                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          194                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          876                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          145                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2560                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.116760                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            75773                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           75773                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         3227                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           36                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           3263                       # number of ReadReq hits
@@ -786,6 +808,15 @@ system.cpu.dcache.tags.warmup_cycle                 0                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  1438.861304                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.351284                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.351284                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1947                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           70                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          432                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1395                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.475342                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         132211530                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        132211530                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     45588097                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        45588097                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     20514029                       # number of WriteReq hits
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
index a8660b22e..4ce0c4345 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -76,16 +81,19 @@ icache_port=system.membus.slave[1]
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
@@ -93,6 +101,7 @@ port=system.membus.slave[4]
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -103,22 +112,26 @@ pio=system.membus.master[1]
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -128,7 +141,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -142,11 +156,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -159,6 +175,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -168,5 +185,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
index 61953e3fc..45d32ca68 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:46:06
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 22:11:10
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 30630542a..bc7c5407d 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.131393                       # Nu
 sim_ticks                                131393279000                       # Number of ticks simulated
 final_tick                               131393279000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1210449                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2028822                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1204235272                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 265804                       # Number of bytes of host memory used
-host_seconds                                   109.11                       # Real time elapsed on the host
+host_inst_rate                                1414135                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2370219                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1406875667                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267896                       # Number of bytes of host memory used
+host_seconds                                    93.39                       # Real time elapsed on the host
 sim_insts                                   132071193                       # Number of instructions simulated
 sim_ops                                     221363385                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        1387954936                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         310423752                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           1698378688                       # Number of bytes read from this memory
@@ -36,6 +38,8 @@ system.physmem.bw_total::total            13685638205                       # To
 system.membus.throughput                  13685638205                       # Throughput (bytes/s)
 system.membus.data_through_bus             1798200879                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
 system.cpu.numCycles                        262786559                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
index 00a43a175..b3c95dee1 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -69,6 +74,7 @@ icache_port=system.cpu.icache.cpu_side
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dcache]
 type=BaseCache
@@ -76,6 +82,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -84,6 +91,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -98,18 +106,22 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
@@ -120,6 +132,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -128,6 +141,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -142,12 +156,15 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -158,16 +175,19 @@ pio=system.membus.master[1]
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
@@ -178,6 +198,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -186,6 +207,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -200,12 +222,15 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -215,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -224,7 +250,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -238,11 +265,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -255,6 +284,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -264,5 +294,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
index e45cd058f..1a4f96712 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
index b436e7f9e..cc37865c7 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:51:48
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 22:12:53
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 9cfd1bb27..2eac3bbbe 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  0.250954                       # Nu
 sim_ticks                                250953957000                       # Number of ticks simulated
 final_tick                               250953957000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 789102                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1322606                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1499404446                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 274284                       # Number of bytes of host memory used
-host_seconds                                   167.37                       # Real time elapsed on the host
+host_inst_rate                                 770398                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1291257                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1463865173                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 276604                       # Number of bytes of host memory used
+host_seconds                                   171.43                       # Real time elapsed on the host
 sim_insts                                   132071193                       # Number of instructions simulated
 sim_ops                                     221363385                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            181760                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            121280                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               303040                       # Number of bytes read from this memory
@@ -44,6 +46,8 @@ system.membus.reqLayer0.occupancy             4753500                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           42633500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
 system.cpu.numCycles                        501907914                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -78,6 +82,15 @@ system.cpu.icache.tags.warmup_cycle                 0                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst  1455.296642                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.710594                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.710594                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1858                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           60                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          498                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          394                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          869                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.907227                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         346993430                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        346993430                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    173489674                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       173489674                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     173489674                       # number of demand (read+write) hits
@@ -160,6 +173,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks     0.000001
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.055847                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.006963                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.062811                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3164                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          513                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          516                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2064                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.096558                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            57590                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           57590                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         1854                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            7                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           1861                       # number of ReadReq hits
@@ -292,6 +314,15 @@ system.cpu.dcache.tags.warmup_cycle                 0                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data  1363.457571                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.332875                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.332875                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1864                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          471                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1328                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.455078                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         154397377                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        154397377                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     56681678                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        56681678                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     20514153                       # number of WriteReq hits
-- 
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