From ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c Mon Sep 17 00:00:00 2001
From: Lisa Hsu <Lisa.Hsu@amd.com>
Date: Thu, 25 Feb 2010 10:08:41 -0800
Subject: stats: update stats for the changes I pushed re: shared cache
 occupancy

---
 .../00.gzip/ref/alpha/tru64/o3-timing/config.ini   |    8 +-
 .../long/00.gzip/ref/alpha/tru64/o3-timing/simout  |    8 +-
 .../00.gzip/ref/alpha/tru64/o3-timing/stats.txt    |   16 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |    2 +-
 .../00.gzip/ref/alpha/tru64/simple-atomic/simout   |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |    8 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |    8 +-
 .../00.gzip/ref/alpha/tru64/simple-timing/simout   |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   16 +-
 .../00.gzip/ref/sparc/linux/o3-timing/config.ini   |    8 +-
 .../long/00.gzip/ref/sparc/linux/o3-timing/simout  |    8 +-
 .../00.gzip/ref/sparc/linux/o3-timing/stats.txt    |   16 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |    2 +-
 .../00.gzip/ref/sparc/linux/simple-atomic/simout   |    8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |    8 +-
 .../ref/sparc/linux/simple-timing/config.ini       |    8 +-
 .../00.gzip/ref/sparc/linux/simple-timing/simout   |    8 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   16 +-
 .../00.gzip/ref/x86/linux/simple-atomic/config.ini |    2 +-
 .../00.gzip/ref/x86/linux/simple-atomic/simout     |    8 +-
 .../00.gzip/ref/x86/linux/simple-atomic/stats.txt  |    8 +-
 .../00.gzip/ref/x86/linux/simple-timing/config.ini |    5 +-
 .../00.gzip/ref/x86/linux/simple-timing/simout     |    8 +-
 .../00.gzip/ref/x86/linux/simple-timing/stats.txt  |   16 +-
 .../ref/alpha/linux/tsunami-o3-dual/config.ini     |   24 +-
 .../ref/alpha/linux/tsunami-o3-dual/simout         |   10 +-
 .../ref/alpha/linux/tsunami-o3-dual/stats.txt      |  621 ++++++++---
 .../ref/alpha/linux/tsunami-o3/config.ini          |   20 +-
 .../ref/alpha/linux/tsunami-o3/simout              |   10 +-
 .../ref/alpha/linux/tsunami-o3/stats.txt           |  394 +++++--
 .../ref/sparc/linux/simple-atomic/config.ini       |    4 +-
 .../10.mcf/ref/sparc/linux/simple-atomic/simout    |    8 +-
 .../10.mcf/ref/sparc/linux/simple-atomic/stats.txt |    8 +-
 .../ref/sparc/linux/simple-timing/config.ini       |   10 +-
 .../10.mcf/ref/sparc/linux/simple-timing/simout    |    8 +-
 .../10.mcf/ref/sparc/linux/simple-timing/stats.txt |   16 +-
 .../10.mcf/ref/x86/linux/simple-atomic/config.ini  |    6 +-
 .../long/10.mcf/ref/x86/linux/simple-atomic/simout |   10 +-
 .../10.mcf/ref/x86/linux/simple-atomic/stats.txt   |    8 +-
 .../10.mcf/ref/x86/linux/simple-timing/config.ini  |    7 +-
 .../long/10.mcf/ref/x86/linux/simple-timing/simout |    8 +-
 .../10.mcf/ref/x86/linux/simple-timing/stats.txt   |   16 +-
 .../ref/x86/linux/simple-atomic/config.ini         |    4 +-
 .../20.parser/ref/x86/linux/simple-atomic/simout   |    8 +-
 .../ref/x86/linux/simple-atomic/stats.txt          |    8 +-
 .../ref/x86/linux/simple-timing/config.ini         |    7 +-
 .../20.parser/ref/x86/linux/simple-timing/simout   |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt          |   16 +-
 .../30.eon/ref/alpha/tru64/o3-timing/config.ini    |   10 +-
 tests/long/30.eon/ref/alpha/tru64/o3-timing/simout |   10 +-
 .../30.eon/ref/alpha/tru64/o3-timing/stats.txt     |   16 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |    2 +-
 .../30.eon/ref/alpha/tru64/simple-atomic/simout    |    8 +-
 .../30.eon/ref/alpha/tru64/simple-atomic/stats.txt |    8 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |    8 +-
 .../30.eon/ref/alpha/tru64/simple-timing/simout    |    8 +-
 .../30.eon/ref/alpha/tru64/simple-timing/stats.txt |   16 +-
 .../ref/alpha/tru64/o3-timing/config.ini           |    8 +-
 .../40.perlbmk/ref/alpha/tru64/o3-timing/simerr    |    2 +-
 .../40.perlbmk/ref/alpha/tru64/o3-timing/simout    |    8 +-
 .../40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt |   16 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |    2 +-
 .../ref/alpha/tru64/simple-atomic/simerr           |    2 +-
 .../ref/alpha/tru64/simple-atomic/simout           |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |    8 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |   10 +-
 .../ref/alpha/tru64/simple-timing/simerr           |    2 +-
 .../ref/alpha/tru64/simple-timing/simout           |   10 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   16 +-
 .../50.vortex/ref/alpha/tru64/o3-timing/config.ini |    8 +-
 .../50.vortex/ref/alpha/tru64/o3-timing/simout     |    8 +-
 .../50.vortex/ref/alpha/tru64/o3-timing/stats.txt  |   16 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |    2 +-
 .../50.vortex/ref/alpha/tru64/simple-atomic/simout |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |    8 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |    8 +-
 .../50.vortex/ref/alpha/tru64/simple-timing/simout |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   16 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |    2 +-
 .../50.vortex/ref/sparc/linux/simple-atomic/simerr | 1122 ++++++++++----------
 .../50.vortex/ref/sparc/linux/simple-atomic/simout |    8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |    8 +-
 .../ref/sparc/linux/simple-timing/config.ini       |    8 +-
 .../50.vortex/ref/sparc/linux/simple-timing/simerr | 1122 ++++++++++----------
 .../50.vortex/ref/sparc/linux/simple-timing/simout |    8 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   16 +-
 .../60.bzip2/ref/alpha/tru64/o3-timing/config.ini  |    8 +-
 .../long/60.bzip2/ref/alpha/tru64/o3-timing/simout |    8 +-
 .../60.bzip2/ref/alpha/tru64/o3-timing/stats.txt   |   18 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |    2 +-
 .../60.bzip2/ref/alpha/tru64/simple-atomic/simout  |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |    8 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |    8 +-
 .../60.bzip2/ref/alpha/tru64/simple-timing/simout  |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   16 +-
 .../ref/x86/linux/simple-atomic/config.ini         |    2 +-
 .../60.bzip2/ref/x86/linux/simple-atomic/simout    |    8 +-
 .../60.bzip2/ref/x86/linux/simple-atomic/stats.txt |    8 +-
 .../ref/x86/linux/simple-timing/config.ini         |    5 +-
 .../60.bzip2/ref/x86/linux/simple-timing/simout    |    8 +-
 .../60.bzip2/ref/x86/linux/simple-timing/stats.txt |   16 +-
 .../70.twolf/ref/alpha/tru64/o3-timing/config.ini  |    8 +-
 .../long/70.twolf/ref/alpha/tru64/o3-timing/simout |   10 +-
 .../70.twolf/ref/alpha/tru64/o3-timing/stats.txt   |   16 +-
 .../ref/alpha/tru64/simple-atomic/config.ini       |    2 +-
 .../70.twolf/ref/alpha/tru64/simple-atomic/simout  |    8 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt        |    8 +-
 .../ref/alpha/tru64/simple-timing/config.ini       |    8 +-
 .../70.twolf/ref/alpha/tru64/simple-timing/simout  |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt        |   16 +-
 .../ref/sparc/linux/simple-atomic/config.ini       |    2 +-
 .../70.twolf/ref/sparc/linux/simple-atomic/simout  |    8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt        |    8 +-
 .../ref/sparc/linux/simple-timing/config.ini       |    8 +-
 .../70.twolf/ref/sparc/linux/simple-timing/simout  |    8 +-
 .../ref/sparc/linux/simple-timing/stats.txt        |   16 +-
 .../ref/x86/linux/simple-atomic/config.ini         |    4 +-
 .../70.twolf/ref/x86/linux/simple-atomic/simout    |   10 +-
 .../70.twolf/ref/x86/linux/simple-atomic/stats.txt |    8 +-
 .../ref/x86/linux/simple-timing/config.ini         |    5 +-
 .../70.twolf/ref/x86/linux/simple-timing/simout    |    8 +-
 .../70.twolf/ref/x86/linux/simple-timing/stats.txt |   16 +-
 .../sparc/solaris/t1000-simple-atomic/config.ini   |   14 +-
 .../ref/sparc/solaris/t1000-simple-atomic/simout   |    8 +-
 .../sparc/solaris/t1000-simple-atomic/stats.txt    |    8 +-
 125 files changed, 2504 insertions(+), 1846 deletions(-)

(limited to 'tests/long')

diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index 96f36a5ca..474c2633d 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -109,7 +109,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -281,7 +281,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -316,7 +316,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -358,7 +358,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
index 8697d1b4d..223344a8e 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul  6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul  6 2009 11:50:56
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:02:05
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index ec3407f13..b56c75dd6 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 305062                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 190836                       # Number of bytes of host memory used
-host_seconds                                  1853.89                       # Real time elapsed on the host
-host_tick_rate                               90122857                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 207071                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 192708                       # Number of bytes of host memory used
+host_seconds                                  2731.20                       # Real time elapsed on the host
+host_tick_rate                               61173967                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   565552443                       # Number of instructions simulated
 sim_seconds                                  0.167078                       # Number of seconds simulated
@@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses           553555                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.999561                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4094.203417                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          152598107                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 29275.574871                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109                       # average overall mshr miss latency
@@ -201,6 +203,8 @@ system.cpu.icache.demand_mshr_misses              902                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.375881                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            769.803945                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses           66014406                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 36214.713430                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029                       # average overall mshr miss latency
@@ -391,6 +395,10 @@ system.cpu.l2cache.demand_mshr_misses          292443                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.051040                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.447409                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1672.465668                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         14660.696789                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            473826                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34265.684253                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143                       # average overall mshr miss latency
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
index af1fb07c3..d1818975e 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
index 760b4567a..d257950b6 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:39:08
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:36:02
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
index ecc08006d..11a5d6497 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                3845310                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 195720                       # Number of bytes of host memory used
-host_seconds                                   156.52                       # Real time elapsed on the host
-host_tick_rate                             1922667398                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1810362                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 184036                       # Number of bytes of host memory used
+host_seconds                                   332.45                       # Real time elapsed on the host
+host_tick_rate                              905187706                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_seconds                                  0.300931                       # Number of seconds simulated
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 014dd0eae..812afa499 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
index 6de92788c..c1023446a 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:05:42
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:27:06
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
index dfa3f12e0..53f0d7951 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2876228                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 205052                       # Number of bytes of host memory used
-host_seconds                                   209.25                       # Real time elapsed on the host
-host_tick_rate                             3718015194                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1555765                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 191800                       # Number of bytes of host memory used
+host_seconds                                   386.86                       # Real time elapsed on the host
+host_tick_rate                             2011092592                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_seconds                                  0.778004                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses           530123                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.999559                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4094.195523                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          153965363                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 42750.401322                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322                       # average overall mshr miss latency
@@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses              795                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.328723                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            673.225223                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          601861898                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -209,6 +213,10 @@ system.cpu.l2cache.demand_mshr_misses          288954                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.050771                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.447994                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1663.663316                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         14679.879055                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            456190                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index b155134f9..4a852e5ff 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -109,7 +109,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -281,7 +281,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -316,7 +316,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -358,7 +358,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
index 80363a0dc..23f626d38 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul  6 2009 11:07:18
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul  6 2009 12:13:14
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:11:32
+M5 executing on SC2B0619
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index 6edc71271..e06d74489 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 146091                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 192556                       # Number of bytes of host memory used
-host_seconds                                  9621.55                       # Real time elapsed on the host
-host_tick_rate                              114603106                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 117151                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 194316                       # Number of bytes of host memory used
+host_seconds                                 11998.32                       # Real time elapsed on the host
+host_tick_rate                               91901100                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1405618365                       # Number of instructions simulated
 sim_seconds                                  1.102659                       # Number of seconds simulated
@@ -103,6 +103,8 @@ system.cpu.dcache.demand_mshr_misses           600222                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.999897                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4095.579742                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          593118564                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 30916.284897                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 23961.331807                       # average overall mshr miss latency
@@ -190,6 +192,8 @@ system.cpu.icache.demand_mshr_misses             1379                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.516598                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1057.993144                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          354588619                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 33291.255289                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059                       # average overall mshr miss latency
@@ -364,6 +368,10 @@ system.cpu.l2cache.demand_mshr_misses          314075                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.055938                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.444640                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1832.969770                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         14569.950583                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            528753                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34273.636870                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.774576                       # average overall mshr miss latency
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
index 92041a7ce..724bab032 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
index c6ea04920..c99734c27 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2009 18:04:32
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:04:58
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:19:07
+M5 executing on SC2B0619
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
index 99ed606e5..d04149323 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2585505                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197792                       # Number of bytes of host memory used
-host_seconds                                   576.11                       # Real time elapsed on the host
-host_tick_rate                             1292756549                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1748575                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 185740                       # Number of bytes of host memory used
+host_seconds                                   851.85                       # Real time elapsed on the host
+host_tick_rate                              874289976                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1489523295                       # Number of instructions simulated
 sim_seconds                                  0.744764                       # Number of seconds simulated
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 2b302db2e..4f8cbe2e9 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
index 224bbd08c..be22dcc27 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:25:44
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:27:10
+M5 executing on SC2B0619
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index 72665606e..89a25e955 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2042056                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 207148                       # Number of bytes of host memory used
-host_seconds                                   729.42                       # Real time elapsed on the host
-host_tick_rate                             2846083906                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 933241                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 193388                       # Number of bytes of host memory used
+host_seconds                                  1596.08                       # Real time elapsed on the host
+host_tick_rate                             1300690172                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1489523295                       # Number of instructions simulated
 sim_seconds                                  2.076001                       # Number of seconds simulated
@@ -60,6 +60,8 @@ system.cpu.dcache.demand_mshr_misses           513081                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.999812                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4095.229973                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          569359660                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 42833.478535                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535                       # average overall mshr miss latency
@@ -113,6 +115,8 @@ system.cpu.icache.demand_mshr_misses             1107                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.442585                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            906.413760                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         1485113012                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55848.238482                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482                       # average overall mshr miss latency
@@ -187,6 +191,10 @@ system.cpu.l2cache.demand_mshr_misses          293479                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.052187                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.447022                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1710.054315                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         14648.032371                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            454328                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
index 8edc68d8c..8ce850818 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
index 4a4332de9..dd9141c9e 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug  8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug  8 2009 12:09:46
-M5 executing on tater
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:41:09
+M5 executing on SC2B0619
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index f1a9425ca..eeabe51c0 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1432576                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 198272                       # Number of bytes of host memory used
-host_seconds                                  1130.39                       # Real time elapsed on the host
-host_tick_rate                              851856908                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1572419                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 188984                       # Number of bytes of host memory used
+host_seconds                                  1029.86                       # Real time elapsed on the host
+host_tick_rate                              935012313                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1619366736                       # Number of instructions simulated
 sim_seconds                                  0.962929                       # Number of seconds simulated
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
index 0c81e9129..c67ff9af1 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -45,6 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -79,6 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -113,6 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -154,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
index 8936a6094..68f564509 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov  8 2009 16:32:22
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:47:37
+M5 executing on SC2B0619
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
index 60806dc72..59d079222 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1181561                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 194380                       # Number of bytes of host memory used
-host_seconds                                  1370.53                       # Real time elapsed on the host
-host_tick_rate                             1324103876                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 992380                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 196544                       # Number of bytes of host memory used
+host_seconds                                  1631.80                       # Real time elapsed on the host
+host_tick_rate                             1112100106                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1619366736                       # Number of instructions simulated
 sim_seconds                                  1.814727                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses           506760                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.999732                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4094.901154                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          607228174                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 42325.964954                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 39325.964954                       # average overall mshr miss latency
@@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses              722                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.322346                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            660.164909                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         1186516703                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -177,6 +181,10 @@ system.cpu.l2cache.demand_mshr_misses          277801                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.052737                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.452189                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1728.087970                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         14817.313734                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            442788                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 7a3c73d3d..803aca1ba 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -8,11 +8,11 @@ type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
 mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -135,7 +135,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -307,7 +307,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -440,7 +440,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -612,7 +612,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -660,7 +660,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -680,7 +680,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -708,7 +708,7 @@ hash_delay=1
 latency=50000
 max_miss_count=0
 mshrs=20
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=500000
@@ -739,7 +739,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=92
-prefetch_cache_check_push=true
+num_cpus=2
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -806,7 +806,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index 79d4b874f..dc5374eea 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul  6 2009 11:02:48
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul  6 2009 11:50:49
-M5 executing on maize
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:13:11
+M5 executing on SC2B0619
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1907705384500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 65f09fbbe..5561f4961 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 195241                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 278896                       # Number of bytes of host memory used
-host_seconds                                   287.80                       # Real time elapsed on the host
-host_tick_rate                             6628539651                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 126888                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 280000                       # Number of bytes of host memory used
+host_seconds                                   442.84                       # Real time elapsed on the host
+host_tick_rate                             4307932213                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    56190549                       # Number of instructions simulated
 sim_seconds                                  1.907705                       # Number of seconds simulated
@@ -49,51 +49,79 @@ system.cpu0.committedInsts                   37660679                       # Nu
 system.cpu0.committedInsts_total             37660679                       # Number of Instructions Simulated
 system.cpu0.cpi                              2.679241                       # CPI: Cycles Per Instruction
 system.cpu0.cpi_total                        2.679241                       # CPI: Total CPI of All Threads
-system.cpu0.dcache.LoadLockedReq_accesses       147686                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15414.654688                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_accesses::0       147686                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       147686                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15414.654688                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.766663                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits          135219                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::0       135219                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       135219                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_miss_latency    192174500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate     0.084416                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses         12467                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.084416                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses::0        12467                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        12467                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_mshr_hits         3210                       # number of LoadLockedReq MSHR hits
 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    109971000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate     0.062680                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.062680                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_misses         9257                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses           6414671                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 28975.322669                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_accesses::0        6414671                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6414671                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 28975.322669                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.577320                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits               5468114                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::0            5468114                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5468114                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_miss_latency   27426794500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate         0.147561                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses              946557                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_miss_rate::0      0.147561                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses::0           946557                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       946557                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_mshr_hits           250848                       # number of ReadReq MSHR hits
 system.cpu0.dcache.ReadReq_mshr_miss_latency  19979077000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate     0.108456                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.108456                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_misses         695709                       # number of ReadReq MSHR misses
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    639862500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses       156551                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency 54668.039693                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_accesses::0       156551                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       156551                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 54668.039693                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51668.039693                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits           140528                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::0        140528                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       140528                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_miss_latency    875946000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate     0.102350                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses          16023                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_miss_rate::0     0.102350                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses::0        16023                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        16023                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency    827877000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate     0.102350                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.102350                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_misses        16023                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses          4258061                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 48857.609099                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_accesses::0       4258061                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4258061                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 48857.609099                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53930.542507                       # average WriteReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits              2612712                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::0           2612712                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       2612712                       # number of WriteReq hits
 system.cpu0.dcache.WriteReq_miss_latency  80387818274                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate        0.386408                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses            1645349                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_miss_rate::0     0.386408                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses::0         1645349                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1645349                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_mshr_hits         1362208                       # number of WriteReq MSHR hits
 system.cpu0.dcache.WriteReq_mshr_miss_latency  15269947736                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate     0.066495                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.066495                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_misses        283141                       # number of WriteReq MSHR misses
 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1050789497                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs  9307.081114                       # average number of cycles each access was blocked
@@ -104,31 +132,57 @@ system.cpu0.dcache.blocked::no_targets              2                       # nu
 system.cpu0.dcache.blocked_cycles::no_mshrs   1082813738                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets        32500                       # number of cycles access was blocked
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.demand_accesses           10672732                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 41596.652338                       # average overall miss latency
+system.cpu0.dcache.demand_accesses::0        10672732                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     10672732                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency::0 41596.652338                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.649983                       # average overall mshr miss latency
-system.cpu0.dcache.demand_hits                8080826                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::0             8080826                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         8080826                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_miss_latency   107814612774                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate          0.242853                       # miss rate for demand accesses
-system.cpu0.dcache.demand_misses              2591906                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_miss_rate::0       0.242853                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu0.dcache.demand_misses::0           2591906                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2591906                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_mshr_hits           1613056                       # number of demand (read+write) MSHR hits
 system.cpu0.dcache.demand_mshr_miss_latency  35249024736                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate     0.091715                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::0     0.091715                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
 system.cpu0.dcache.demand_mshr_misses          978850                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses          10672732                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 41596.652338                       # average overall miss latency
+system.cpu0.dcache.occ_%::0                  0.863629                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::0           442.178159                       # Average occupied blocks per context
+system.cpu0.dcache.overall_accesses::0       10672732                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     10672732                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency::0 41596.652338                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.649983                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits               8080826                       # number of overall hits
+system.cpu0.dcache.overall_hits::0            8080826                       # number of overall hits
+system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        8080826                       # number of overall hits
 system.cpu0.dcache.overall_miss_latency  107814612774                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate         0.242853                       # miss rate for overall accesses
-system.cpu0.dcache.overall_misses             2591906                       # number of overall misses
+system.cpu0.dcache.overall_miss_rate::0      0.242853                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu0.dcache.overall_misses::0          2591906                       # number of overall misses
+system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2591906                       # number of overall misses
 system.cpu0.dcache.overall_mshr_hits          1613056                       # number of overall MSHR hits
 system.cpu0.dcache.overall_mshr_miss_latency  35249024736                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate     0.091715                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::0     0.091715                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_misses         978850                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_uncacheable_latency   1690651997                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -192,16 +246,23 @@ system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Nu
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::total            70526783                       # Number of instructions fetched each cycle (Total)
-system.cpu0.icache.ReadReq_accesses           6456937                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 15194.125887                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_accesses::0        6456937                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      6456937                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency::0 15194.125887                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.650508                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits               5806694                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::0            5806694                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        5806694                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_miss_latency    9879873999                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate         0.100705                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses              650243                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_miss_rate::0      0.100705                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses::0           650243                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       650243                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_mshr_hits            29877                       # number of ReadReq MSHR hits
 system.cpu0.icache.ReadReq_mshr_miss_latency   7526063499                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate     0.096077                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.096077                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_misses         620366                       # number of ReadReq MSHR misses
 system.cpu0.icache.avg_blocked_cycles::no_mshrs 11808.794118                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
@@ -211,31 +272,57 @@ system.cpu0.icache.blocked::no_targets              0                       # nu
 system.cpu0.icache.blocked_cycles::no_mshrs       401499                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.demand_accesses            6456937                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 15194.125887                       # average overall miss latency
+system.cpu0.icache.demand_accesses::0         6456937                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      6456937                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency::0 15194.125887                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu0.icache.demand_avg_mshr_miss_latency 12131.650508                       # average overall mshr miss latency
-system.cpu0.icache.demand_hits                5806694                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::0             5806694                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         5806694                       # number of demand (read+write) hits
 system.cpu0.icache.demand_miss_latency     9879873999                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate          0.100705                       # miss rate for demand accesses
-system.cpu0.icache.demand_misses               650243                       # number of demand (read+write) misses
+system.cpu0.icache.demand_miss_rate::0       0.100705                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu0.icache.demand_misses::0            650243                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        650243                       # number of demand (read+write) misses
 system.cpu0.icache.demand_mshr_hits             29877                       # number of demand (read+write) MSHR hits
 system.cpu0.icache.demand_mshr_miss_latency   7526063499                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate     0.096077                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::0     0.096077                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_misses          620366                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.overall_accesses           6456937                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 15194.125887                       # average overall miss latency
+system.cpu0.icache.occ_%::0                  0.995760                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::0           509.829037                       # Average occupied blocks per context
+system.cpu0.icache.overall_accesses::0        6456937                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      6456937                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency::0 15194.125887                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency 12131.650508                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits               5806694                       # number of overall hits
+system.cpu0.icache.overall_hits::0            5806694                       # number of overall hits
+system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.icache.overall_hits::total        5806694                       # number of overall hits
 system.cpu0.icache.overall_miss_latency    9879873999                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate         0.100705                       # miss rate for overall accesses
-system.cpu0.icache.overall_misses              650243                       # number of overall misses
+system.cpu0.icache.overall_miss_rate::0      0.100705                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu0.icache.overall_misses::0           650243                       # number of overall misses
+system.cpu0.icache.overall_misses::1                0                       # number of overall misses
+system.cpu0.icache.overall_misses::total       650243                       # number of overall misses
 system.cpu0.icache.overall_mshr_hits            29877                       # number of overall MSHR hits
 system.cpu0.icache.overall_mshr_miss_latency   7526063499                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate     0.096077                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::0     0.096077                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_misses         620366                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -515,51 +602,79 @@ system.cpu1.committedInsts                   18529870                       # Nu
 system.cpu1.committedInsts_total             18529870                       # Number of Instructions Simulated
 system.cpu1.cpi                              2.312190                       # CPI: Cycles Per Instruction
 system.cpu1.cpi_total                        2.312190                       # CPI: Total CPI of All Threads
-system.cpu1.dcache.LoadLockedReq_accesses        72126                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency 14445.783133                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_accesses::0        72126                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        72126                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14445.783133                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11202.181535                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits           59842                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::0        59842                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        59842                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_miss_latency    177452000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate     0.170313                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses         12284                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.170313                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses::0        12284                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        12284                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_mshr_hits         2016                       # number of LoadLockedReq MSHR hits
 system.cpu1.dcache.LoadLockedReq_mshr_miss_latency    115024000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate     0.142362                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.142362                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_misses        10268                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses           3589394                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency 15546.336868                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_accesses::0        3589394                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3589394                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency::0 15546.336868                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12022.349090                       # average ReadReq mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits               2947184                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::0            2947184                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        2947184                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_miss_latency    9984013000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate         0.178919                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses              642210                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_miss_rate::0      0.178919                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses::0           642210                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       642210                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_mshr_hits           211141                       # number of ReadReq MSHR hits
 system.cpu1.dcache.ReadReq_mshr_miss_latency   5182462000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate     0.120095                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.120095                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_misses         431069                       # number of ReadReq MSHR misses
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency    298578500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.StoreCondReq_accesses        68169                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency 54676.100066                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_accesses::0        68169                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        68169                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 54676.100066                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51676.100066                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits            51420                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::0         51420                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        51420                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_miss_latency    915770000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate     0.245698                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses          16749                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_miss_rate::0     0.245698                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses::0        16749                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        16749                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_mshr_miss_latency    865523000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate     0.245698                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.245698                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_misses        16749                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses          2234886                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency 49366.459666                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_accesses::0       2234886                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2234886                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency::0 49366.459666                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54247.809571                       # average WriteReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits              1540754                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::0           1540754                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1540754                       # number of WriteReq hits
 system.cpu1.dcache.WriteReq_miss_latency  34266839381                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate        0.310589                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses             694132                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_miss_rate::0     0.310589                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses::0          694132                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       694132                       # number of WriteReq misses
 system.cpu1.dcache.WriteReq_mshr_hits          551528                       # number of WriteReq MSHR hits
 system.cpu1.dcache.WriteReq_mshr_miss_latency   7735954636                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate     0.063808                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.063808                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_mshr_misses        142604                       # number of WriteReq MSHR misses
 system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    526038500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13994.026145                       # average number of cycles each access was blocked
@@ -570,31 +685,59 @@ system.cpu1.dcache.blocked::no_targets              1                       # nu
 system.cpu1.dcache.blocked_cycles::no_mshrs    438908636                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets         5000                       # number of cycles access was blocked
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.demand_accesses            5824280                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 33113.418856                       # average overall miss latency
+system.cpu1.dcache.demand_accesses::0         5824280                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      5824280                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency::0 33113.418856                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu1.dcache.demand_avg_mshr_miss_latency 22518.780971                       # average overall mshr miss latency
-system.cpu1.dcache.demand_hits                4487938                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::0             4487938                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         4487938                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_miss_latency    44250852381                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate          0.229443                       # miss rate for demand accesses
-system.cpu1.dcache.demand_misses              1336342                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_miss_rate::0       0.229443                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu1.dcache.demand_misses::0           1336342                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       1336342                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_mshr_hits            762669                       # number of demand (read+write) MSHR hits
 system.cpu1.dcache.demand_mshr_miss_latency  12918416636                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate     0.098497                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::0     0.098497                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_misses          573673                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.overall_accesses           5824280                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 33113.418856                       # average overall miss latency
+system.cpu1.dcache.occ_%::0                  0.953247                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_%::1                 -0.003823                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::0           488.062339                       # Average occupied blocks per context
+system.cpu1.dcache.occ_blocks::1            -1.957577                       # Average occupied blocks per context
+system.cpu1.dcache.overall_accesses::0        5824280                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      5824280                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency::0 33113.418856                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency 22518.780971                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits               4487938                       # number of overall hits
+system.cpu1.dcache.overall_hits::0            4487938                       # number of overall hits
+system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        4487938                       # number of overall hits
 system.cpu1.dcache.overall_miss_latency   44250852381                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate         0.229443                       # miss rate for overall accesses
-system.cpu1.dcache.overall_misses             1336342                       # number of overall misses
+system.cpu1.dcache.overall_miss_rate::0      0.229443                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu1.dcache.overall_misses::0          1336342                       # number of overall misses
+system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      1336342                       # number of overall misses
 system.cpu1.dcache.overall_mshr_hits           762669                       # number of overall MSHR hits
 system.cpu1.dcache.overall_mshr_miss_latency  12918416636                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate     0.098497                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::0     0.098497                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_misses         573673                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_uncacheable_latency    824617000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -658,16 +801,23 @@ system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Nu
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::total            38118943                       # Number of instructions fetched each cycle (Total)
-system.cpu1.icache.ReadReq_accesses           3089103                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency 14554.957905                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_accesses::0        3089103                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      3089103                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency::0 14554.957905                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11604.745633                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits               2620972                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::0            2620972                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        2620972                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_miss_latency    6813626999                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate         0.151543                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses              468131                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_miss_rate::0      0.151543                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses::0           468131                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       468131                       # number of ReadReq misses
 system.cpu1.icache.ReadReq_mshr_hits            20962                       # number of ReadReq MSHR hits
 system.cpu1.icache.ReadReq_mshr_miss_latency   5189282500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate     0.144757                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.144757                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_mshr_misses         447169                       # number of ReadReq MSHR misses
 system.cpu1.icache.avg_blocked_cycles::no_mshrs 11057.692308                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
@@ -677,31 +827,57 @@ system.cpu1.icache.blocked::no_targets              0                       # nu
 system.cpu1.icache.blocked_cycles::no_mshrs       287500                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.demand_accesses            3089103                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 14554.957905                       # average overall miss latency
+system.cpu1.icache.demand_accesses::0         3089103                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      3089103                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency::0 14554.957905                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu1.icache.demand_avg_mshr_miss_latency 11604.745633                       # average overall mshr miss latency
-system.cpu1.icache.demand_hits                2620972                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::0             2620972                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         2620972                       # number of demand (read+write) hits
 system.cpu1.icache.demand_miss_latency     6813626999                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate          0.151543                       # miss rate for demand accesses
-system.cpu1.icache.demand_misses               468131                       # number of demand (read+write) misses
+system.cpu1.icache.demand_miss_rate::0       0.151543                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu1.icache.demand_misses::0            468131                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        468131                       # number of demand (read+write) misses
 system.cpu1.icache.demand_mshr_hits             20962                       # number of demand (read+write) MSHR hits
 system.cpu1.icache.demand_mshr_miss_latency   5189282500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate     0.144757                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::0     0.144757                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
 system.cpu1.icache.demand_mshr_misses          447169                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.overall_accesses           3089103                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency 14554.957905                       # average overall miss latency
+system.cpu1.icache.occ_%::0                  0.985305                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_blocks::0           504.476148                       # Average occupied blocks per context
+system.cpu1.icache.overall_accesses::0        3089103                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      3089103                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency::0 14554.957905                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency 11604.745633                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits               2620972                       # number of overall hits
+system.cpu1.icache.overall_hits::0            2620972                       # number of overall hits
+system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.icache.overall_hits::total        2620972                       # number of overall hits
 system.cpu1.icache.overall_miss_latency    6813626999                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate         0.151543                       # miss rate for overall accesses
-system.cpu1.icache.overall_misses              468131                       # number of overall misses
+system.cpu1.icache.overall_miss_rate::0      0.151543                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu1.icache.overall_misses::0           468131                       # number of overall misses
+system.cpu1.icache.overall_misses::1                0                       # number of overall misses
+system.cpu1.icache.overall_misses::total       468131                       # number of overall misses
 system.cpu1.icache.overall_mshr_hits            20962                       # number of overall MSHR hits
 system.cpu1.icache.overall_mshr_miss_latency   5189282500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate     0.144757                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::0     0.144757                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
 system.cpu1.icache.overall_mshr_misses         447169                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -931,23 +1107,35 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iocache.ReadReq_accesses                   175                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_avg_miss_latency  115331.417143                       # average ReadReq miss latency
+system.iocache.ReadReq_accesses::1                175                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115331.417143                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency 63331.417143                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_miss_latency          20182998                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_rate                    1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses                     175                       # number of ReadReq misses
+system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses::1                  175                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
 system.iocache.ReadReq_mshr_miss_latency     11082998                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate               1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_misses                175                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency 137844.166490                       # average WriteReq miss latency
+system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137844.166490                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency 85840.579852                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_miss_latency       5727700806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
+system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
 system.iocache.WriteReq_mshr_miss_latency   3566847774                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_rate              1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
 system.iocache.avg_blocked_cycles::no_mshrs  6165.982406                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
@@ -957,31 +1145,57 @@ system.iocache.blocked::no_targets                  0                       # nu
 system.iocache.blocked_cycles::no_mshrs      64483844                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.demand_accesses                  41727                       # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency   137749.749658                       # average overall miss latency
+system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1               41727                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41727                       # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137749.749658                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.iocache.demand_avg_mshr_miss_latency 85746.178062                       # average overall mshr miss latency
-system.iocache.demand_hits                          0                       # number of demand (read+write) hits
+system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
 system.iocache.demand_miss_latency         5747883804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
-system.iocache.demand_misses                    41727                       # number of demand (read+write) misses
+system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
+system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                 41727                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
 system.iocache.demand_mshr_miss_latency    3577930772                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate                1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_misses               41727                       # number of demand (read+write) MSHR misses
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.overall_accesses                 41727                       # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency  137749.749658                       # average overall miss latency
+system.iocache.occ_%::1                      0.024239                       # Average percentage of cache occupancy
+system.iocache.occ_blocks::1                 0.387817                       # Average occupied blocks per context
+system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1              41727                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137749.749658                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.iocache.overall_avg_mshr_miss_latency 85746.178062                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.overall_hits                         0                       # number of overall hits
+system.iocache.overall_hits::0                      0                       # number of overall hits
+system.iocache.overall_hits::1                      0                       # number of overall hits
+system.iocache.overall_hits::total                  0                       # number of overall hits
 system.iocache.overall_miss_latency        5747883804                       # number of overall miss cycles
-system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
-system.iocache.overall_misses                   41727                       # number of overall misses
+system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
+system.iocache.overall_misses::0                    0                       # number of overall misses
+system.iocache.overall_misses::1                41727                       # number of overall misses
+system.iocache.overall_misses::total            41727                       # number of overall misses
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
 system.iocache.overall_mshr_miss_latency   3577930772                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate               1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_misses              41727                       # number of overall MSHR misses
 system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -992,41 +1206,78 @@ system.iocache.tagsinuse                     0.387817                       # Cy
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.warmup_cycle              1717170531000                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41522                       # number of writebacks
-system.l2c.ReadExReq_accesses                  317502                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency    52375.571804                       # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0               221647                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                95855                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           317502                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 75026.275109                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 173484.417078                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency 40223.037770                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_miss_latency         16629348799                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses                    317502                       # number of ReadExReq misses
+system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 221647                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                  95855                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             317502                       # number of ReadExReq misses
 system.l2c.ReadExReq_mshr_miss_latency    12770894938                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate                 1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       1.432467                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1       3.312315                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_misses               317502                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses                   2204779                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency      51979.602997                       # average ReadReq miss latency
+system.l2c.ReadReq_accesses::0                1321671                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                 883108                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2204779                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   53351.845432                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   2020931.340670                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency 39977.821348                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits                       1893900                       # number of ReadReq hits
+system.l2c.ReadReq_hits::0                    1018788                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                     875112                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1893900                       # number of ReadReq hits
 system.l2c.ReadReq_miss_latency           16159367000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate                 0.141002                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses                      310879                       # number of ReadReq misses
+system.l2c.ReadReq_miss_rate::0              0.229167                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.009054                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                   302883                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                     7996                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               310879                       # number of ReadReq misses
 system.l2c.ReadReq_mshr_hits                       17                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_miss_latency      12427585500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate            0.140995                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::0         0.235204                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         0.352009                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_misses                 310862                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_uncacheable_latency    840472000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses                 141949                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency   51066.182164                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_accesses::0               78396                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1               63553                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          141949                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 92463.818205                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 114059.029346                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.290548                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_miss_latency         7248793492                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses                   141949                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_miss_rate::0                  1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                 78396                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                 63553                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total            141949                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_mshr_miss_latency    5691202500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate                1                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0      1.810666                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1      2.233553                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_misses              141949                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.WriteReq_mshr_uncacheable_latency   1423763998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses                  455578                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits                      455578                       # number of Writeback hits
+system.l2c.Writeback_accesses::0               455578                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           455578                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   455578                       # number of Writeback hits
+system.l2c.Writeback_hits::total               455578                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.avg_refs                          4.834791                       # Average number of references to valid blocks.
@@ -1035,31 +1286,73 @@ system.l2c.blocked::no_targets                      0                       # nu
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses                    2522281                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency       52179.674113                       # average overall miss latency
+system.l2c.demand_accesses::0                 1543318                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                  978963                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2522281                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    62510.658683                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    315728.455181                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.l2c.demand_avg_mshr_miss_latency  40101.725175                       # average overall mshr miss latency
-system.l2c.demand_hits                        1893900                       # number of demand (read+write) hits
+system.l2c.demand_hits::0                     1018788                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      875112                       # number of demand (read+write) hits
+system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1893900                       # number of demand (read+write) hits
 system.l2c.demand_miss_latency            32788715799                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate                  0.249132                       # miss rate for demand accesses
-system.l2c.demand_misses                       628381                       # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0               0.339872                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.106083                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
+system.l2c.demand_misses::0                    524530                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                    103851                       # number of demand (read+write) misses
+system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                628381                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                        17                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_miss_latency       25198480438                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate             0.249125                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::0          0.407151                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          0.641867                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_misses                  628364                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.overall_accesses                   2522281                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency      52179.674113                       # average overall miss latency
+system.l2c.occ_%::0                          0.065210                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.029545                       # Average percentage of cache occupancy
+system.l2c.occ_%::2                          0.380758                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                  4273.595958                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                  1936.249784                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                 24953.333071                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                1543318                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                 978963                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2522281                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   62510.658683                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   315728.455181                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.l2c.overall_avg_mshr_miss_latency 40101.725175                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits                       1893900                       # number of overall hits
+system.l2c.overall_hits::0                    1018788                       # number of overall hits
+system.l2c.overall_hits::1                     875112                       # number of overall hits
+system.l2c.overall_hits::2                          0                       # number of overall hits
+system.l2c.overall_hits::total                1893900                       # number of overall hits
 system.l2c.overall_miss_latency           32788715799                       # number of overall miss cycles
-system.l2c.overall_miss_rate                 0.249132                       # miss rate for overall accesses
-system.l2c.overall_misses                      628381                       # number of overall misses
+system.l2c.overall_miss_rate::0              0.339872                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.106083                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
+system.l2c.overall_misses::0                   524530                       # number of overall misses
+system.l2c.overall_misses::1                   103851                       # number of overall misses
+system.l2c.overall_misses::2                        0                       # number of overall misses
+system.l2c.overall_misses::total               628381                       # number of overall misses
 system.l2c.overall_mshr_hits                       17                       # number of overall MSHR hits
 system.l2c.overall_mshr_miss_latency      25198480438                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate            0.249125                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::0         0.407151                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         0.641867                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_misses                 628364                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_latency   2264235998                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 0dba7f9ef..6eea1f6ec 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -8,11 +8,11 @@ type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
 mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -135,7 +135,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -307,7 +307,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=4
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -355,7 +355,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -375,7 +375,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -403,7 +403,7 @@ hash_delay=1
 latency=50000
 max_miss_count=0
 mshrs=20
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=500000
@@ -434,7 +434,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=92
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -501,7 +501,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index 553916200..00e25aeac 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul  6 2009 11:02:48
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul  6 2009 11:50:49
-M5 executing on maize
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:35:15
+M5 executing on SC2B0619
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1867362977500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index de748ed07..75071ea91 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 193554                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 276972                       # Number of bytes of host memory used
-host_seconds                                   274.29                       # Real time elapsed on the host
-host_tick_rate                             6807960214                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  86499                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 277924                       # Number of bytes of host memory used
+host_seconds                                   613.76                       # Real time elapsed on the host
+host_tick_rate                             3042478511                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    53090223                       # Number of instructions simulated
 sim_seconds                                  1.867363                       # Number of seconds simulated
@@ -49,51 +49,79 @@ system.cpu.committedInsts                    53090223                       # Nu
 system.cpu.committedInsts_total              53090223                       # Number of Instructions Simulated
 system.cpu.cpi                               2.580471                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         2.580471                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses       214422                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 15515.537615                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses::0       214422                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       214422                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.537615                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.147928                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits           192250                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::0        192250                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       192250                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_miss_latency    344010500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate     0.103404                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses          22172                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_miss_rate::0     0.103404                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0        22172                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22172                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_mshr_hits         4650                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency    207007500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.081717                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.081717                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_misses        17522                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses            9342386                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 23884.018523                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses::0         9342386                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9342386                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 23884.018523                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22765.012818                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits                7810012                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::0             7810012                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7810012                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_miss_latency    36599249000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.164024                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1532374                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_miss_rate::0       0.164024                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0           1532374                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1532374                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_mshr_hits            447551                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_miss_latency  24696009500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.116118                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.116118                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses         1084823                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency    904976000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses        219797                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.488950                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_accesses::0       219797                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       219797                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56331.488950                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.488950                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits            189796                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::0         189796                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       189796                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_miss_latency   1690001000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_rate     0.136494                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses           30001                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_miss_rate::0     0.136494                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses::0        30001                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total        30001                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_mshr_miss_latency   1599998000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_rate     0.136494                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.136494                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_misses        30001                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses           6157245                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 49037.572489                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses::0        6157245                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6157245                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 49037.572489                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54494.404609                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits               3926713                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::0            3926713                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        3926713                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_miss_latency  109379874638                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.362261                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             2230532                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_miss_rate::0      0.362261                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0          2230532                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2230532                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_mshr_hits          1833591                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_miss_latency  21631063460                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.064467                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.064467                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses         396941                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1235842997                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.dcache.avg_blocked_cycles::no_mshrs 10022.289139                       # average number of cycles each access was blocked
@@ -104,31 +132,57 @@ system.cpu.dcache.blocked::no_targets               4                       # nu
 system.cpu.dcache.blocked_cycles::no_mshrs   1373885462                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets        66000                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            15499631                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 38794.252006                       # average overall miss latency
+system.cpu.dcache.demand_accesses::0         15499631                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15499631                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 38794.252006                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency 31264.812048                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                11736725                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::0             11736725                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         11736725                       # number of demand (read+write) hits
 system.cpu.dcache.demand_miss_latency    145979123638                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.242774                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               3762906                       # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate::0        0.242774                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses::0            3762906                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3762906                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits            2281142                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_miss_latency  46327072960                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.095600                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::0     0.095600                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses          1481764                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses           15499631                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 38794.252006                       # average overall miss latency
+system.cpu.dcache.occ_%::0                   0.999991                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0            511.995450                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses::0        15499631                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15499631                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::0 38794.252006                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 31264.812048                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               11736725                       # number of overall hits
+system.cpu.dcache.overall_hits::0            11736725                       # number of overall hits
+system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::total        11736725                       # number of overall hits
 system.cpu.dcache.overall_miss_latency   145979123638                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.242774                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              3762906                       # number of overall misses
+system.cpu.dcache.overall_miss_rate::0       0.242774                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses::0           3762906                       # number of overall misses
+system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3762906                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits           2281142                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_miss_latency  46327072960                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.095600                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::0     0.095600                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses         1481764                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency   2140818997                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -192,16 +246,23 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total            102272708                       # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses            8997144                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 14906.743449                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_accesses::0         8997144                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8997144                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::0 14906.743449                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.437092                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits                7949609                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::0             7949609                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7949609                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency    15615335499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.116430                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses              1047535                       # number of ReadReq misses
+system.cpu.icache.ReadReq_miss_rate::0       0.116430                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0           1047535                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1047535                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_hits             51877                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_miss_latency  11855735000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.110664                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.110664                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses          995658                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs 11545.454545                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
@@ -211,31 +272,57 @@ system.cpu.icache.blocked::no_targets               0                       # nu
 system.cpu.icache.blocked_cycles::no_mshrs       635000                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses             8997144                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 14906.743449                       # average overall miss latency
+system.cpu.icache.demand_accesses::0          8997144                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8997144                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::0 14906.743449                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 11907.437092                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                 7949609                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::0              7949609                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7949609                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency     15615335499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.116430                       # miss rate for demand accesses
-system.cpu.icache.demand_misses               1047535                       # number of demand (read+write) misses
+system.cpu.icache.demand_miss_rate::0        0.116430                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.icache.demand_misses::0            1047535                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1047535                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits              51877                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency  11855735000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.110664                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::0     0.110664                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses           995658                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses            8997144                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 14906.743449                       # average overall miss latency
+system.cpu.icache.occ_%::0                   0.995649                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            509.772438                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses::0         8997144                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8997144                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::0 14906.743449                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 11907.437092                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits                7949609                       # number of overall hits
+system.cpu.icache.overall_hits::0             7949609                       # number of overall hits
+system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::total         7949609                       # number of overall hits
 system.cpu.icache.overall_miss_latency    15615335499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.116430                       # miss rate for overall accesses
-system.cpu.icache.overall_misses              1047535                       # number of overall misses
+system.cpu.icache.overall_miss_rate::0       0.116430                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.icache.overall_misses::0           1047535                       # number of overall misses
+system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::total       1047535                       # number of overall misses
 system.cpu.icache.overall_mshr_hits             51877                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency  11855735000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.110664                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::0     0.110664                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses          995658                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -482,23 +569,35 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iocache.ReadReq_accesses                   173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_avg_miss_latency  115260.104046                       # average ReadReq miss latency
+system.iocache.ReadReq_accesses::1                173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115260.104046                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_miss_latency          19939998                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_rate                    1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses                     173                       # number of ReadReq misses
+system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses::1                  173                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.ReadReq_mshr_miss_latency     10943998                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate               1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_misses                173                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency 137794.253129                       # average WriteReq miss latency
+system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137794.253129                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency 85790.836302                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_miss_latency       5725626806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
+system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
 system.iocache.WriteReq_mshr_miss_latency   3564780830                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_rate              1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
 system.iocache.avg_blocked_cycles::no_mshrs  6161.136802                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
@@ -508,31 +607,57 @@ system.iocache.blocked::no_targets                  0                       # nu
 system.iocache.blocked_cycles::no_mshrs      64537908                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.demand_accesses                  41725                       # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency   137700.822145                       # average overall miss latency
+system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1               41725                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137700.822145                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.iocache.demand_avg_mshr_miss_latency 85697.419485                       # average overall mshr miss latency
-system.iocache.demand_hits                          0                       # number of demand (read+write) hits
+system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
 system.iocache.demand_miss_latency         5745566804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
-system.iocache.demand_misses                    41725                       # number of demand (read+write) misses
+system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
+system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                 41725                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
 system.iocache.demand_mshr_miss_latency    3575724828                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate                1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_misses               41725                       # number of demand (read+write) MSHR misses
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.overall_accesses                 41725                       # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency  137700.822145                       # average overall miss latency
+system.iocache.occ_%::1                      0.079213                       # Average percentage of cache occupancy
+system.iocache.occ_blocks::1                 1.267415                       # Average occupied blocks per context
+system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1              41725                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137700.822145                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.iocache.overall_avg_mshr_miss_latency 85697.419485                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.overall_hits                         0                       # number of overall hits
+system.iocache.overall_hits::0                      0                       # number of overall hits
+system.iocache.overall_hits::1                      0                       # number of overall hits
+system.iocache.overall_hits::total                  0                       # number of overall hits
 system.iocache.overall_miss_latency        5745566804                       # number of overall miss cycles
-system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
-system.iocache.overall_misses                   41725                       # number of overall misses
+system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
+system.iocache.overall_misses::0                    0                       # number of overall misses
+system.iocache.overall_misses::1                41725                       # number of overall misses
+system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
 system.iocache.overall_mshr_miss_latency   3575724828                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate               1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_misses              41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -543,41 +668,62 @@ system.iocache.tagsinuse                     1.267415                       # Cy
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.warmup_cycle              1716179713000                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41512                       # number of writebacks
-system.l2c.ReadExReq_accesses                  300582                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency    52361.965557                       # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0               300582                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           300582                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 52361.965557                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency 40206.978448                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_miss_latency         15739064331                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses                    300582                       # number of ReadExReq misses
+system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 300582                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             300582                       # number of ReadExReq misses
 system.l2c.ReadExReq_mshr_miss_latency    12085493996                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate                 1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0              1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_misses               300582                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses                   2097743                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency      52046.745492                       # average ReadReq miss latency
+system.l2c.ReadReq_accesses::0                2097743                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2097743                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   52046.745492                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1            inf                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency 40015.135689                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits                       1786590                       # number of ReadReq hits
+system.l2c.ReadReq_hits::0                    1786590                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1786590                       # number of ReadReq hits
 system.l2c.ReadReq_miss_latency           16194501000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate                 0.148328                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses                      311153                       # number of ReadReq misses
+system.l2c.ReadReq_miss_rate::0              0.148328                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                   311153                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               311153                       # number of ReadReq misses
 system.l2c.ReadReq_mshr_hits                        1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_miss_latency      12450789500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate            0.148327                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::0         0.148327                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1              inf                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_misses                 311152                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_uncacheable_latency    810515500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses                 130274                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency   52273.201045                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_accesses::0              130274                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          130274                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 52273.201045                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.567435                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_miss_latency         6809838993                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses                   130274                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_miss_rate::0                  1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                130274                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total            130274                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_mshr_miss_latency    5223670500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate                1                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0             1                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_misses              130274                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.WriteReq_mshr_uncacheable_latency   1116273498                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses                  430447                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits                      430447                       # number of Writeback hits
+system.l2c.Writeback_accesses::0               430447                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           430447                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   430447                       # number of Writeback hits
+system.l2c.Writeback_hits::total               430447                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.avg_refs                          4.597861                       # Average number of references to valid blocks.
@@ -586,31 +732,59 @@ system.l2c.blocked::no_targets                      0                       # nu
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses                    2398325                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency       52201.631966                       # average overall miss latency
+system.l2c.demand_accesses::0                 2398325                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2398325                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    52201.631966                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1             inf                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.l2c.demand_avg_mshr_miss_latency  40109.399667                       # average overall mshr miss latency
-system.l2c.demand_hits                        1786590                       # number of demand (read+write) hits
+system.l2c.demand_hits::0                     1786590                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1786590                       # number of demand (read+write) hits
 system.l2c.demand_miss_latency            31933565331                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate                  0.255068                       # miss rate for demand accesses
-system.l2c.demand_misses                       611735                       # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0               0.255068                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
+system.l2c.demand_misses::0                    611735                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                611735                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                         1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_miss_latency       24536283496                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate             0.255067                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::0          0.255067                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1               inf                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_misses                  611734                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.overall_accesses                   2398325                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency      52201.631966                       # average overall miss latency
+system.l2c.occ_%::0                          0.090392                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.377907                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                  5923.908547                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 24766.488602                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                2398325                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2398325                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   52201.631966                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1            inf                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.l2c.overall_avg_mshr_miss_latency 40109.399667                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits                       1786590                       # number of overall hits
+system.l2c.overall_hits::0                    1786590                       # number of overall hits
+system.l2c.overall_hits::1                          0                       # number of overall hits
+system.l2c.overall_hits::total                1786590                       # number of overall hits
 system.l2c.overall_miss_latency           31933565331                       # number of overall miss cycles
-system.l2c.overall_miss_rate                 0.255068                       # miss rate for overall accesses
-system.l2c.overall_misses                      611735                       # number of overall misses
+system.l2c.overall_miss_rate::0              0.255068                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
+system.l2c.overall_misses::0                   611735                       # number of overall misses
+system.l2c.overall_misses::1                        0                       # number of overall misses
+system.l2c.overall_misses::total               611735                       # number of overall misses
 system.l2c.overall_mshr_hits                        1                       # number of overall MSHR hits
 system.l2c.overall_mshr_miss_latency      24536283496                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate            0.255067                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::0         0.255067                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1              inf                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_misses                 611734                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_latency   1926788998                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index 93528e180..d56440ca5 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -57,9 +57,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
index 529f20a79..6c4e0d9c5 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2009 18:04:32
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:06:05
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:27:41
+M5 executing on SC2B0619
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index ce9766cbc..2eefb0962 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2430508                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 329972                       # Number of bytes of host memory used
-host_seconds                                   100.32                       # Real time elapsed on the host
-host_tick_rate                             1218223693                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1458389                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 317928                       # Number of bytes of host memory used
+host_seconds                                   167.20                       # Real time elapsed on the host
+host_tick_rate                              730976871                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   243835278                       # Number of instructions simulated
 sim_seconds                                  0.122216                       # Number of seconds simulated
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index 676b1ef8d..b6cfae717 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -157,9 +157,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
index 431d9905a..80c9b27b1 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:30:43
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:30:29
+M5 executing on SC2B0619
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 803a77546..5683e9007 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1809872                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 339332                       # Number of bytes of host memory used
-host_seconds                                   134.73                       # Real time elapsed on the host
-host_tick_rate                             2719868473                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 794629                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 325576                       # Number of bytes of host memory used
+host_seconds                                   306.85                       # Real time elapsed on the host
+host_tick_rate                             1194166006                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   243835278                       # Number of instructions simulated
 sim_seconds                                  0.366435                       # Number of seconds simulated
@@ -60,6 +60,8 @@ system.cpu.dcache.demand_mshr_misses           987820                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.871490                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           3569.622607                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          105122385                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 18046.382944                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944                       # average overall mshr miss latency
@@ -113,6 +115,8 @@ system.cpu.icache.demand_mshr_misses              882                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.354611                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            726.242454                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          244421512                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55904.761905                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905                       # average overall mshr miss latency
@@ -187,6 +191,10 @@ system.cpu.l2cache.demand_mshr_misses           47800                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.010976                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.262444                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           359.659901                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          8599.756547                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            940453                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
index 7c74336b4..662e9141e 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -52,14 +52,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
index faf614c2c..f9e963c82 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 17 2009 20:29:57
-M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch
-M5 started Aug 17 2009 20:30:53
-M5 executing on tater
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:50:08
+M5 executing on SC2B0619
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index 16f0b4a6b..0cb316cbf 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 635652                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 347576                       # Number of bytes of host memory used
-host_seconds                                   424.28                       # Real time elapsed on the host
-host_tick_rate                              388188748                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1130966                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 323116                       # Number of bytes of host memory used
+host_seconds                                   238.47                       # Real time elapsed on the host
+host_tick_rate                              690673696                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   269695959                       # Number of instructions simulated
 sim_seconds                                  0.164702                       # Number of seconds simulated
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
index c90ba3ccf..14d594ef3 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -45,6 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -79,6 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -113,6 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -154,9 +157,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
index 035c663f2..3d3eaa281 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov  8 2009 16:34:05
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:52:35
+M5 executing on SC2B0619
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
index b582ff405..5338d200d 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 839358                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 328912                       # Number of bytes of host memory used
-host_seconds                                   321.31                       # Real time elapsed on the host
-host_tick_rate                             1189158712                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 855655                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 331116                       # Number of bytes of host memory used
+host_seconds                                   315.19                       # Real time elapsed on the host
+host_tick_rate                             1212247082                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   269695959                       # Number of instructions simulated
 sim_seconds                                  0.382091                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses          2195642                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.995395                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4077.137530                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          122219193                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 20188.783508                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 17188.783508                       # average overall mshr miss latency
@@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses              808                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.325918                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            667.480800                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          217696172                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -177,6 +181,10 @@ system.cpu.l2cache.demand_mshr_misses          195509                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.198854                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.350512                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          6516.062046                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         11485.589337                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           2067619                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 52000.158560                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
index 5b5021cae..e58df7993 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -57,9 +57,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
index d34525ab8..1c2b2b54d 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug  8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug  8 2009 12:09:45
-M5 executing on tater
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:53:46
+M5 executing on SC2B0619
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 54f4e25be..e3dcb1667 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1252342                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 201956                       # Number of bytes of host memory used
-host_seconds                                  1194.32                       # Real time elapsed on the host
-host_tick_rate                              727261872                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1408369                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 192628                       # Number of bytes of host memory used
+host_seconds                                  1062.01                       # Real time elapsed on the host
+host_tick_rate                              817869724                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1495700470                       # Number of instructions simulated
 sim_seconds                                  0.868585                       # Number of seconds simulated
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
index a7ed66f8a..c8eb88a42 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -45,6 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -79,6 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -113,6 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -154,9 +157,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
index a11db4e1e..458afbc15 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov  8 2009 16:39:28
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:54:07
+M5 executing on SC2B0619
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
index 0e665b6ef..87bf15b21 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1459378                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 198104                       # Number of bytes of host memory used
-host_seconds                                  1024.89                       # Real time elapsed on the host
-host_tick_rate                             1680505604                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 925832                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200280                       # Number of bytes of host memory used
+host_seconds                                  1615.52                       # Real time elapsed on the host
+host_tick_rate                             1066115675                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1495700470                       # Number of instructions simulated
 sim_seconds                                  1.722332                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses          3192703                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.997757                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4086.814341                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          533262382                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 38769.912986                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 35769.912360                       # average overall mshr miss latency
@@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses             2814                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.433368                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            887.538461                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         1068347073                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 48626.865672                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 45626.865672                       # average overall mshr miss latency
@@ -177,6 +181,10 @@ system.cpu.l2cache.demand_mshr_misses         1210961                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.111890                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.413414                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          3666.426168                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         13546.751396                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           2521227                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 52000.009497                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 561928f24..ef5381d49 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -109,7 +109,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -281,7 +281,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -316,7 +316,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -353,12 +353,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
+cwd=build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
index 319145d66..84704aca2 100755
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul  6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul  6 2009 11:50:56
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
+M5 compiled Feb 24 2010 23:12:54
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:18:35
+M5 executing on SC2B0619
+command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 31281b132..86e5c6d82 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 241043                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197116                       # Number of bytes of host memory used
-host_seconds                                  1558.12                       # Real time elapsed on the host
-host_tick_rate                               86640473                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 119207                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 198920                       # Number of bytes of host memory used
+host_seconds                                  3150.62                       # Real time elapsed on the host
+host_tick_rate                               42847667                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   375574819                       # Number of instructions simulated
 sim_seconds                                  0.134997                       # Number of seconds simulated
@@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses             4293                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.804192                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           3293.970402                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          169022038                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 30545.726047                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145                       # average overall mshr miss latency
@@ -201,6 +203,8 @@ system.cpu.icache.demand_mshr_misses             3896                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.890401                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1823.540410                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses           63866189                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 32249.018798                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563                       # average overall mshr miss latency
@@ -391,6 +395,10 @@ system.cpu.l2cache.demand_mshr_misses            7418                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.106709                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.011557                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          3496.652993                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           378.690415                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses              8073                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34461.782017                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336                       # average overall mshr miss latency
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index 193b9744b..c17ad3a43 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
index ff24c9828..799b8b93c 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:39:12
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:33:35
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index 2dd6bb319..79a1d3a15 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                3427488                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203296                       # Number of bytes of host memory used
-host_seconds                                   116.31                       # Real time elapsed on the host
-host_tick_rate                             1713741057                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1825585                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 190564                       # Number of bytes of host memory used
+host_seconds                                   218.38                       # Real time elapsed on the host
+host_tick_rate                              912792158                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_seconds                                  0.199332                       # Number of seconds simulated
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
index cb9992f60..9f3658fe3 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
index c7ba9a351..15db5ae30 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:06:21
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:20:32
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 5933cded2..f93d01d91 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2382679                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 212620                       # Number of bytes of host memory used
-host_seconds                                   167.32                       # Real time elapsed on the host
-host_tick_rate                             3390857898                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 860135                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 198216                       # Number of bytes of host memory used
+host_seconds                                   463.49                       # Real time elapsed on the host
+host_tick_rate                             1224083493                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_seconds                                  0.567352                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses             4264                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.802954                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           3288.899192                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          168275220                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 54847.560976                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976                       # average overall mshr miss latency
@@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses             3673                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.876526                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1795.124700                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          398664666                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 50648.516199                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199                       # average overall mshr miss latency
@@ -209,6 +213,10 @@ system.cpu.l2cache.demand_mshr_misses            7240                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.101996                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.011352                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          3342.203160                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           371.972955                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses              7825                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 451db988f..a58d921a8 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -109,7 +109,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -281,7 +281,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -316,7 +316,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -358,7 +358,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
index 01b34fd92..f8c1ec2f3 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
@@ -1,4 +1,4 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: ignoring syscall sigprocmask(0, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index ab163e0dc..6590e3c76 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul  6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul  6 2009 11:52:13
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:45:31
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 6f8327e62..6efaa543d 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 233856                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197400                       # Number of bytes of host memory used
-host_seconds                                  7795.57                       # Real time elapsed on the host
-host_tick_rate                               90456464                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 178423                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199584                       # Number of bytes of host memory used
+host_seconds                                 10217.56                       # Real time elapsed on the host
+host_tick_rate                               69014447                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1823043370                       # Number of instructions simulated
 sim_seconds                                  0.705159                       # Number of seconds simulated
@@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses          1534074                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.999781                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4095.104513                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          676532165                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 37782.429340                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909                       # average overall mshr miss latency
@@ -201,6 +203,8 @@ system.cpu.icache.demand_mshr_misses             9768                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.788136                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1614.102824                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          348447899                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 15851.065828                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514                       # average overall mshr miss latency
@@ -391,6 +395,10 @@ system.cpu.l2cache.demand_mshr_misses         1511777                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.927694                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.046416                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         30398.691034                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          1520.954518                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           1540711                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34361.852641                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313                       # average overall mshr miss latency
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index d69895fd2..09e561461 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
index 01b34fd92..f8c1ec2f3 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
@@ -1,4 +1,4 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: ignoring syscall sigprocmask(0, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index 867a8e254..2679d4b08 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:41:45
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:10:59
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index 587f67841..93699388f 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                3366150                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202468                       # Number of bytes of host memory used
-host_seconds                                   596.82                       # Real time elapsed on the host
-host_tick_rate                             1683437750                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2073139                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 190360                       # Number of bytes of host memory used
+host_seconds                                   969.06                       # Real time elapsed on the host
+host_tick_rate                             1036792835                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_seconds                                  1.004711                       # Number of seconds simulated
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 066cbfff7..8af60fc8a 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -152,12 +152,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
index 01b34fd92..f8c1ec2f3 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
@@ -1,4 +1,4 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: ignoring syscall sigprocmask(0, 1, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index 81c2e87d9..effc9024e 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:09:09
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
+M5 compiled Feb 24 2010 23:12:54
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 01:51:28
+M5 executing on SC2B0619
+command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 93430ba50..f1307660f 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2471520                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211800                       # Number of bytes of host memory used
-host_seconds                                   812.86                       # Real time elapsed on the host
-host_tick_rate                             3463041314                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1237577                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 198020                       # Number of bytes of host memory used
+host_seconds                                  1623.32                       # Real time elapsed on the host
+host_tick_rate                             1734066560                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_seconds                                  2.814951                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses          1532979                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.999804                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4095.198740                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          721864922                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 55421.867488                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 52421.867488                       # average overall mshr miss latency
@@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses            10596                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.721885                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1478.420115                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         2009421071                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 23421.857305                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305                       # average overall mshr miss latency
@@ -209,6 +213,10 @@ system.cpu.l2cache.demand_mshr_misses         1511420                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.926943                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.046880                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         30374.076068                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          1536.161417                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           1540740                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 33c06f76d..821bc3ec9 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -109,7 +109,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -281,7 +281,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -316,7 +316,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -358,7 +358,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 84d8d4369..dddba13b1 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul  6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul  6 2009 11:55:23
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:28:19
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 254fb17d5..d2ad10f5b 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 254468                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 199708                       # Number of bytes of host memory used
-host_seconds                                   312.78                       # Real time elapsed on the host
-host_tick_rate                               86754409                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 172212                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201796                       # Number of bytes of host memory used
+host_seconds                                   462.17                       # Real time elapsed on the host
+host_tick_rate                               58711424                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_seconds                                  0.027135                       # Number of seconds simulated
@@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses           211325                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.995440                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4077.324152                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           35038890                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 32023.260673                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222                       # average overall mshr miss latency
@@ -201,6 +203,8 @@ system.cpu.icache.demand_mshr_misses            85936                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.936032                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1916.994169                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses           13386072                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency  9527.179672                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  6037.865388                       # average overall mshr miss latency
@@ -391,6 +395,10 @@ system.cpu.l2cache.demand_mshr_misses          188071                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.089962                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.474123                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2947.876007                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15536.049051                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            290965                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34290.353106                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275                       # average overall mshr miss latency
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index 31e1868d0..4900adf7c 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
index 9dd7f1f1a..23a9c78bc 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:57:23
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:20:31
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index aa4c8889a..365160857 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                5366735                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 205860                       # Number of bytes of host memory used
-host_seconds                                    16.46                       # Real time elapsed on the host
-host_tick_rate                             2686413423                       # Simulator tick rate (ticks/s)
+host_inst_rate                                3163275                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 192676                       # Number of bytes of host memory used
+host_seconds                                    27.93                       # Real time elapsed on the host
+host_tick_rate                             1583437342                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_seconds                                  0.044221                       # Number of seconds simulated
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index f5ae96163..8ecb2b7e9 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
index 0cf74eb02..5b5245d37 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:10:15
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:21:01
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index cc2716377..3f747beae 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2287584                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215192                       # Number of bytes of host memory used
-host_seconds                                    38.62                       # Real time elapsed on the host
-host_tick_rate                             3500174868                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1182325                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200332                       # Number of bytes of host memory used
+host_seconds                                    74.72                       # Real time elapsed on the host
+host_tick_rate                             1809050434                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_seconds                                  0.135169                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses           210559                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.995818                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4078.872537                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           34890015                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 50768.948371                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371                       # average overall mshr miss latency
@@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses            76436                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.913950                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1871.768668                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses           88438074                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 18810.691297                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297                       # average overall mshr miss latency
@@ -209,6 +213,10 @@ system.cpu.l2cache.demand_mshr_misses          186875                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.081795                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.475328                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2680.267907                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15575.557767                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            280780                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index f0c5c3a9b..f7d6c90f7 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr
index b33f4f1d5..f0135998f 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr
@@ -1,1125 +1,1125 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall time(4026527848, 4026528248, ...)
+warn: ignoring syscall time(4026528248, 4026527848, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527400, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026527400, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527312, 1, ...)
+warn: ignoring syscall time(1, 4026527312, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 413, ...)
+warn: ignoring syscall time(413, 4026527048, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 414, ...)
+warn: ignoring syscall time(414, 4026527048, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527288, 4026527688, ...)
+warn: ignoring syscall time(4026527688, 4026527288, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526840, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026526840, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526960, 409, ...)
+warn: ignoring syscall time(409, 4026526960, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527040, 409, ...)
+warn: ignoring syscall time(409, 4026527040, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527000, 409, ...)
+warn: ignoring syscall time(409, 4026527000, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526984, 409, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526984, 409, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526312, 19045, ...)
+warn: ignoring syscall time(19045, 4026526312, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526832, 409, ...)
+warn: ignoring syscall time(409, 4026526832, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526848, 409, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526840, 409, ...)
+warn: ignoring syscall time(409, 4026526840, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526848, 409, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526936, 409, ...)
+warn: ignoring syscall time(409, 4026526936, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527008, 4026527408, ...)
+warn: ignoring syscall time(4026527408, 4026527008, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526560, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026526560, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527184, 18732, ...)
+warn: ignoring syscall time(18732, 4026527184, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526632, 409, ...)
+warn: ignoring syscall time(409, 4026526632, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526736, 0, ...)
+warn: ignoring syscall time(0, 4026526736, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527320, 0, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527744, 225, ...)
+warn: ignoring syscall time(225, 4026527744, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527096, 4026527496, ...)
+warn: ignoring syscall time(4026527496, 4026527096, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526648, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026526648, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526824, 0, ...)
+warn: ignoring syscall time(0, 4026526824, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527320, 0, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527184, 1879089152, ...)
+warn: ignoring syscall time(1879089152, 4026527184, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 1595768, ...)
+warn: ignoring syscall time(1595768, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 17300, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 19045, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 19045, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 17300, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026525968, 20500, ...)
+warn: ignoring syscall time(20500, 4026525968, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026525968, 4026526436, ...)
+warn: ignoring syscall time(4026526436, 4026525968, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526056, 7004192, ...)
+warn: ignoring syscall time(7004192, 4026526056, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527512, 4, ...)
+warn: ignoring syscall time(4, 4026527512, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026525760, 0, ...)
+warn: ignoring syscall time(0, 4026525760, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
index 736241b6c..27a5cc38b 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2009 18:04:32
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:05:08
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:33:19
+M5 executing on SC2B0619
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index aa22e4be1..b6b56aac5 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2400032                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206680                       # Number of bytes of host memory used
-host_seconds                                    56.72                       # Real time elapsed on the host
-host_tick_rate                             1201405231                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1397341                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 194632                       # Number of bytes of host memory used
+host_seconds                                    97.43                       # Real time elapsed on the host
+host_tick_rate                              699480350                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136139203                       # Number of instructions simulated
 sim_seconds                                  0.068149                       # Number of seconds simulated
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 67702eb09..ace2091d8 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr
index b33f4f1d5..f0135998f 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr
@@ -1,1125 +1,1125 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: ignoring syscall time(4026527848, 4026528248, ...)
+warn: ignoring syscall time(4026528248, 4026527848, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527400, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026527400, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527312, 1, ...)
+warn: ignoring syscall time(1, 4026527312, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 413, ...)
+warn: ignoring syscall time(413, 4026527048, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 414, ...)
+warn: ignoring syscall time(414, 4026527048, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527288, 4026527688, ...)
+warn: ignoring syscall time(4026527688, 4026527288, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526840, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026526840, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526960, 409, ...)
+warn: ignoring syscall time(409, 4026526960, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527040, 409, ...)
+warn: ignoring syscall time(409, 4026527040, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527000, 409, ...)
+warn: ignoring syscall time(409, 4026527000, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526984, 409, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526984, 409, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526312, 19045, ...)
+warn: ignoring syscall time(19045, 4026526312, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526832, 409, ...)
+warn: ignoring syscall time(409, 4026526832, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526848, 409, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526840, 409, ...)
+warn: ignoring syscall time(409, 4026526840, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526848, 409, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526936, 409, ...)
+warn: ignoring syscall time(409, 4026526936, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527008, 4026527408, ...)
+warn: ignoring syscall time(4026527408, 4026527008, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526560, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026526560, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527184, 18732, ...)
+warn: ignoring syscall time(18732, 4026527184, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526632, 409, ...)
+warn: ignoring syscall time(409, 4026526632, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526736, 0, ...)
+warn: ignoring syscall time(0, 4026526736, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527320, 0, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527744, 225, ...)
+warn: ignoring syscall time(225, 4026527744, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527096, 4026527496, ...)
+warn: ignoring syscall time(4026527496, 4026527096, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526648, 1375098, ...)
+warn: ignoring syscall time(1375098, 4026526648, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526824, 0, ...)
+warn: ignoring syscall time(0, 4026526824, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527320, 0, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527184, 1879089152, ...)
+warn: ignoring syscall time(1879089152, 4026527184, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 1595768, ...)
+warn: ignoring syscall time(1595768, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 17300, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 19045, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 19045, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526912, 17300, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026525968, 20500, ...)
+warn: ignoring syscall time(20500, 4026525968, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026525968, 4026526436, ...)
+warn: ignoring syscall time(4026526436, 4026525968, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026526056, 7004192, ...)
+warn: ignoring syscall time(7004192, 4026526056, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026527512, 4, ...)
+warn: ignoring syscall time(4, 4026527512, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
-warn: ignoring syscall time(4026525760, 0, ...)
+warn: ignoring syscall time(0, 4026525760, ...)
 For more information see: http://www.m5sim.org/warn/5c5b547f
 hack: be nice to actually delete the event here
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
index ccf7882ed..0431d5fd8 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:31:17
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:34:57
+M5 executing on SC2B0619
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 9bb41084a..fe7329cf3 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1881110                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 216040                       # Number of bytes of host memory used
-host_seconds                                    72.37                       # Real time elapsed on the host
-host_tick_rate                             2810156861                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 755710                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202292                       # Number of bytes of host memory used
+host_seconds                                   180.15                       # Real time elapsed on the host
+host_tick_rate                             1128944281                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136139203                       # Number of instructions simulated
 sim_seconds                                  0.203377                       # Number of seconds simulated
@@ -60,6 +60,8 @@ system.cpu.dcache.demand_mshr_misses           154904                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.997952                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4087.609698                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           58095605                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 50895.212519                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519                       # average overall mshr miss latency
@@ -113,6 +115,8 @@ system.cpu.icache.demand_mshr_misses           187024                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.978865                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           2004.715107                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          134553584                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 16936.029600                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600                       # average overall mshr miss latency
@@ -187,6 +191,10 @@ system.cpu.l2cache.demand_mshr_misses          144925                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.120206                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.469380                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          3938.922202                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15380.640176                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            337702                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index f540ab7a3..b5c8ed0d7 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -109,7 +109,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -281,7 +281,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -316,7 +316,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -358,7 +358,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 26e42fa14..9f955a134 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 22 2009 13:11:07
-M5 revision e406bb83c56f 6682 default qtip tip syscall-ioctl.patch
-M5 started Oct 22 2009 13:42:59
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:37:14
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index d858d0b22..411912baf 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 254978                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 190768                       # Number of bytes of host memory used
-host_seconds                                  6808.60                       # Real time elapsed on the host
-host_tick_rate                              109025257                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 176404                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 192532                       # Number of bytes of host memory used
+host_seconds                                  9841.32                       # Real time elapsed on the host
+host_tick_rate                               75427820                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_seconds                                  0.742309                       # Number of seconds simulated
@@ -103,6 +103,10 @@ system.cpu.dcache.demand_mshr_misses          9523666                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.997499                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_%::1                  -0.003145                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4085.757368                       # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::1            -12.883149                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          683988466                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 22764.945466                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 17378.935401                       # average overall mshr miss latency
@@ -209,6 +213,8 @@ system.cpu.icache.demand_mshr_misses              902                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.347376                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            711.425375                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          355180518                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 35446.920583                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282                       # average overall mshr miss latency
@@ -399,6 +405,10 @@ system.cpu.l2cache.demand_mshr_misses         3773319                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.453663                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.336804                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         14865.634361                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         11036.400552                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           9160773                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34457.219077                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618                       # average overall mshr miss latency
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index 4a349e817..8eb2ad76d 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
index 3b9fb39a4..b436e5a76 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:59:02
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:01:37
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index 81d14da53..279d75547 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                3729984                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 195632                       # Number of bytes of host memory used
-host_seconds                                   487.88                       # Real time elapsed on the host
-host_tick_rate                             1871753572                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1736234                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 184024                       # Number of bytes of host memory used
+host_seconds                                  1048.12                       # Real time elapsed on the host
+host_tick_rate                              871264314                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_seconds                                  0.913189                       # Number of seconds simulated
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index fd5428b3a..dc20618d9 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 154e8b6b0..34965adea 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:13:47
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:20:02
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 106a8a8a6..a48cc62c7 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2540644                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204972                       # Number of bytes of host memory used
-host_seconds                                   716.27                       # Real time elapsed on the host
-host_tick_rate                             3808619272                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1190978                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 191664                       # Number of bytes of host memory used
+host_seconds                                  1527.97                       # Real time elapsed on the host
+host_tick_rate                             1785366772                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_seconds                                  2.727991                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses          9470216                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.996068                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4079.892573                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          605324165                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 32281.622404                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404                       # average overall mshr miss latency
@@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses              802                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.298700                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            611.737435                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         1826378510                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -209,6 +213,10 @@ system.cpu.l2cache.demand_mshr_misses         3764493                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.438454                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.335641                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         14367.257286                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         10998.286802                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           9112536                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 8cd09b7fa..d7e2d0edd 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
index 583e2baa8..84cb84ccc 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug  8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug  8 2009 12:09:46
-M5 executing on tater
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:57:51
+M5 executing on SC2B0619
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 8024dc3cd..46cb78389 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1851230                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 198160                       # Number of bytes of host memory used
-host_seconds                                  2513.64                       # Real time elapsed on the host
-host_tick_rate                             1125554314                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1880958                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 188832                       # Number of bytes of host memory used
+host_seconds                                  2473.91                       # Real time elapsed on the host
+host_tick_rate                             1143628848                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  4653327894                       # Number of instructions simulated
 sim_seconds                                  2.829240                       # Number of seconds simulated
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
index d5c949c6e..734089aa9 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -45,6 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -79,6 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -113,6 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -154,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
index 8e0139bb7..8794a16bf 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov  8 2009 16:30:56
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:58:19
+M5 executing on SC2B0619
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index ffd34c1e6..d56c14beb 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1485872                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 194272                       # Number of bytes of host memory used
-host_seconds                                  3131.72                       # Real time elapsed on the host
-host_tick_rate                             1912063349                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1049992                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 196480                       # Number of bytes of host memory used
+host_seconds                                  4431.78                       # Real time elapsed on the host
+host_tick_rate                             1351159917                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  4653327894                       # Number of instructions simulated
 sim_seconds                                  5.988038                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses          9469303                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.997259                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4084.774232                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses         1677713078                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 32370.287021                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 29370.287021                       # average overall mshr miss latency
@@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses              675                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.271276                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            555.573148                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         4013232890                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -177,6 +181,10 @@ system.cpu.l2cache.demand_mshr_misses         3785130                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.437806                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.347809                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         14346.014207                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         11397.001683                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           9112667                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index f62e1fe85..5dc5abaaf 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -109,7 +109,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -281,7 +281,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -316,7 +316,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -358,7 +358,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
index 226a69a68..ce84b73e7 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -5,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul  6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul  6 2009 12:07:21
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:44:07
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
-Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
-Couldn't unlink  build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 5e3b32f0d..96c3646b7 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 203956                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 194360                       # Number of bytes of host memory used
-host_seconds                                   412.73                       # Real time elapsed on the host
-host_tick_rate                               98897987                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  80276                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 196620                       # Number of bytes of host memory used
+host_seconds                                  1048.63                       # Real time elapsed on the host
+host_tick_rate                               38925589                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_seconds                                  0.040819                       # Number of seconds simulated
@@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses             2357                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.356054                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           1458.398369                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           29903525                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 35255.314688                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289                       # average overall mshr miss latency
@@ -201,6 +203,8 @@ system.cpu.icache.demand_mshr_misses            10056                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.753902                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1543.991602                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses           19230003                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 15782.750498                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589                       # average overall mshr miss latency
@@ -391,6 +395,10 @@ system.cpu.l2cache.demand_mshr_misses            5110                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.068091                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.000414                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2231.205034                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1            13.564546                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses             12296                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 34416.438356                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139                       # average overall mshr miss latency
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 1107790b1..fb69f2147 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
index 76511d754..5acd06099 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:51:42
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:01:12
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index b041df4e4..cb61596f5 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                5612458                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 200556                       # Number of bytes of host memory used
-host_seconds                                    16.38                       # Real time elapsed on the host
-host_tick_rate                             2806199168                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1794306                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 187928                       # Number of bytes of host memory used
+host_seconds                                    51.22                       # Real time elapsed on the host
+host_tick_rate                              897149357                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_seconds                                  0.045952                       # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 7b97859d0..2e720b950 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
index 723d89b16..927d0a698 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:16:45
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:41:35
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index 557fc7bf7..ab73f2477 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2678753                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 209892                       # Number of bytes of host memory used
-host_seconds                                    34.31                       # Real time elapsed on the host
-host_tick_rate                             3461170696                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 611509                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195576                       # Number of bytes of host memory used
+host_seconds                                   150.29                       # Real time elapsed on the host
+host_tick_rate                              790125098                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_seconds                                  0.118747                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses             2334                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.352056                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           1442.022508                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 55046.272494                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494                       # average overall mshr miss latency
@@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses             8510                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.692396                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1418.025998                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses           91903090                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 26935.605170                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170                       # average overall mshr miss latency
@@ -209,6 +213,10 @@ system.cpu.l2cache.demand_mshr_misses            4791                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.061290                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.000419                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2008.334369                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1            13.724981                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses             10733                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index a9a96bdd5..4873f314b 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
index 473c9fb4d..30e9edddf 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2009 18:04:32
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:14:36
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:35:37
+M5 executing on SC2B0619
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index a32d620ce..ec86f0831 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2403614                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 202316                       # Number of bytes of host memory used
-host_seconds                                    80.48                       # Real time elapsed on the host
-host_tick_rate                             1201810632                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1979245                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 190260                       # Number of bytes of host memory used
+host_seconds                                    97.74                       # Real time elapsed on the host
+host_tick_rate                              989625806                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193444769                       # Number of instructions simulated
 sim_seconds                                  0.096723                       # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
index d52807b10..fb6af19fc 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -45,7 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -80,7 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -115,7 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
index 4ba32ea3a..04fab7689 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 22 2009 06:58:47
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:32:30
-M5 executing on maize
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:37:15
+M5 executing on SC2B0619
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index ce58f98ef..791de009c 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1857648                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211672                       # Number of bytes of host memory used
-host_seconds                                   104.13                       # Real time elapsed on the host
-host_tick_rate                             2598354088                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 890462                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197912                       # Number of bytes of host memory used
+host_seconds                                   217.24                       # Real time elapsed on the host
+host_tick_rate                             1245520491                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193444769                       # Number of instructions simulated
 sim_seconds                                  0.270578                       # Number of seconds simulated
@@ -60,6 +60,8 @@ system.cpu.dcache.demand_mshr_misses             1599                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.302049                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           1237.193190                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           76711508                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -113,6 +115,8 @@ system.cpu.icache.demand_mshr_misses            12288                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.777132                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1591.566647                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          193445549                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 26294.433594                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594                       # average overall mshr miss latency
@@ -187,6 +191,10 @@ system.cpu.l2cache.demand_mshr_misses            5173                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.081095                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.000000                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2657.327524                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             0.000455                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses             13864                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
index 4d458b23f..77f906a7d 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -52,12 +52,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
+cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
index 1b109ceb4..d0e32b9a8 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 17 2009 20:29:57
-M5 revision 84f7bdc43a4f 6605 default qtip tip x86fsdate.patch
-M5 started Aug 17 2009 20:37:58
-M5 executing on tater
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 04:02:03
+M5 executing on SC2B0619
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index d9b5a344c..556a9fb7a 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 608858                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 220444                       # Number of bytes of host memory used
-host_seconds                                   360.40                       # Real time elapsed on the host
-host_tick_rate                              361897269                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1408387                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 196212                       # Number of bytes of host memory used
+host_seconds                                   155.80                       # Real time elapsed on the host
+host_tick_rate                              837126295                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   219430973                       # Number of instructions simulated
 sim_seconds                                  0.130427                       # Number of seconds simulated
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
index 6cbe3be3b..57a70ac98 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -45,6 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -79,6 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -113,6 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -154,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
index 32ad08600..517f22714 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov  8 2009 16:37:25
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 04:04:39
+M5 executing on SC2B0619
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 96e63da4b..512b20d78 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 894535                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 201656                       # Number of bytes of host memory used
-host_seconds                                   245.30                       # Real time elapsed on the host
-host_tick_rate                             1023073835                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 527252                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203888                       # Number of bytes of host memory used
+host_seconds                                   416.18                       # Real time elapsed on the host
+host_tick_rate                              603014388                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   219430973                       # Number of instructions simulated
 sim_seconds                                  0.250962                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses             1928                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.332384                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           1361.446792                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           77197730                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 55870.331950                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 52870.072614                       # average overall mshr miss latency
@@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses             4694                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.710588                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1455.283940                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          173494375                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 39420.856412                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718                       # average overall mshr miss latency
@@ -177,6 +181,10 @@ system.cpu.l2cache.demand_mshr_misses            4736                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.062047                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.000001                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2033.146081                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             0.022985                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses              6596                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency 52003.272804                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index b6c350b4c..4c20f32d0 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -9,25 +9,25 @@ children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_
 boot_cpu_frequency=1
 boot_osflags=a
 hypervisor_addr=1099243257856
-hypervisor_bin=/dist/m5/system/binaries/q_new.bin
+hypervisor_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/q_new.bin
 hypervisor_desc=system.hypervisor_desc
 hypervisor_desc_addr=133446500352
-hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
+hypervisor_desc_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/1up-hv.bin
 init_param=0
 kernel=
 mem_mode=atomic
 nvram=system.nvram
 nvram_addr=133429198848
-nvram_bin=/dist/m5/system/binaries/nvram1
+nvram_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/nvram1
 openboot_addr=1099243716608
-openboot_bin=/dist/m5/system/binaries/openboot_new.bin
+openboot_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/openboot_new.bin
 partition_desc=system.partition_desc
 partition_desc_addr=133445976064
-partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
+partition_desc_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/1up-md.bin
 physmem=system.physmem
 readfile=tests/halt.sh
 reset_addr=1099243192320
-reset_bin=/dist/m5/system/binaries/reset_new.bin
+reset_bin=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/reset_new.bin
 rom=system.rom
 symbolfile=
 
@@ -110,7 +110,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/disk.s10hw2
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/disk.s10hw2
 read_only=true
 
 [system.hypervisor_desc]
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index 655c95551..fc75aba24 100755
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 21 2009 18:38:50
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 18:39:20
-M5 executing on zizzer
+M5 compiled Feb 25 2010 03:38:31
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:38:45
+M5 executing on SC2B0619
 command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
 Global frequency set at 2000000000 ticks per second
 info: No kernel set for full system simulation. Assuming you know what you're doing...
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index 044bdb674..16e4b5160 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2338829                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 501616                       # Number of bytes of host memory used
-host_seconds                                   953.11                       # Real time elapsed on the host
-host_tick_rate                                2343672                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2688852                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 490548                       # Number of bytes of host memory used
+host_seconds                                   829.04                       # Real time elapsed on the host
+host_tick_rate                                2694420                       # Simulator tick rate (ticks/s)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
 sim_insts                                  2229160714                       # Number of instructions simulated
 sim_seconds                                  1.116889                       # Number of seconds simulated
-- 
cgit v1.2.3