From 45f881919fc9c4d2b2d4ea9f165fb567aad9849a Mon Sep 17 00:00:00 2001 From: Brad Beckmann Date: Sun, 6 Feb 2011 22:14:23 -0800 Subject: regress: Regression Tester output updates --- tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt') diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index be248d562..311784102 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 36108 # Simulator instruction rate (inst/s) -host_mem_usage 155860 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 125462283 # Simulator tick rate (ticks/s) +host_inst_rate 43704 # Simulator instruction rate (inst/s) +host_mem_usage 205152 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host +host_tick_rate 151823848 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000022 # Number of seconds simulated @@ -267,6 +267,8 @@ system.cpu.l2cache.total_refs 1 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.numCycles 44578 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.runCycles 7154 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -- cgit v1.2.3