From 257e09d62622676b84b5166854850024a5f72bcc Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 5 Nov 2006 20:42:05 -0500 Subject: Update refs. --HG-- extra : convert_revision : 61d298fb0d9a66a76209a6bfcdb7c14f2efca947 --- tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini') diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index f8e1f1bb0..d8fc14e8d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -64,7 +64,6 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache progress_interval=0 system=system workload=system.cpu.workload @@ -78,7 +77,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -118,7 +116,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -158,7 +155,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -195,6 +191,7 @@ mem_side=system.membus.port[1] type=Bus bus_id=0 clock=1000 +responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side @@ -217,6 +214,7 @@ uid=100 type=Bus bus_id=0 clock=1000 +responder_set=false width=64 port=system.physmem.port system.cpu.l2cache.mem_side -- cgit v1.2.3