From 8833b4cd44457d50b45a4dfe642cdb5e51c0889d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 26 Feb 2008 02:20:40 -0500 Subject: Bus: Update the stats for the recent bus fix. --HG-- extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407 --- tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini | 3 +++ 1 file changed, 3 insertions(+) (limited to 'tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini') diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 78fe6c01f..7b95a328d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -152,6 +152,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side @@ -169,6 +170,7 @@ euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 @@ -180,6 +182,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.l2cache.mem_side -- cgit v1.2.3