From d272bdb1bf409ed06d7c2d8bcea47f88de990759 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Tue, 10 Jan 2012 17:28:49 -0600 Subject: MOESI Hammer: Update regression test output --- .../simple-timing-ruby-MOESI_hammer/ruby.stats | 130 ++++++++++----------- 1 file changed, 63 insertions(+), 67 deletions(-) (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats') diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats index 2bf189137..b81839414 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Apr/28/2011 15:12:18 +Real time: Jan/10/2012 12:42:00 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.36 -Virtual_time_in_minutes: 0.006 -Virtual_time_in_hours: 0.0001 -Virtual_time_in_days: 4.16667e-06 +Virtual_time_in_seconds: 0.21 +Virtual_time_in_minutes: 0.0035 +Virtual_time_in_hours: 5.83333e-05 +Virtual_time_in_days: 2.43056e-06 Ruby_current_time: 78448 Ruby_start_time: 0 Ruby_cycles: 78448 -mbytes_resident: 37.8359 -mbytes_total: 220.914 -resident_ratio: 0.171323 +mbytes_resident: 37.832 +mbytes_total: 233.867 +resident_ratio: 0.161817 ruby_cycles_executed: [ 78449 ] @@ -126,7 +126,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10907 +page_reclaims: 10644 page_faults: 0 swaps: 0 block_inputs: 0 @@ -181,28 +181,28 @@ links_utilized_percent_switch_2: 2.15844 outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.cpu_ruby_ports.icache - system.ruby.cpu_ruby_ports.icache_total_misses: 270 - system.ruby.cpu_ruby_ports.icache_total_demand_misses: 270 - system.ruby.cpu_ruby_ports.icache_total_prefetches: 0 - system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0 - system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 270 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 - system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100% + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor: 270 100% + system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 270 100% -Cache Stats: system.ruby.cpu_ruby_ports.dcache - system.ruby.cpu_ruby_ports.dcache_total_misses: 240 - system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 240 - system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 240 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 240 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.cpu_ruby_ports.dcache_request_type_LD: 75.8333% - system.ruby.cpu_ruby_ports.dcache_request_type_ST: 24.1667% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 75.8333% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 24.1667% - system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 240 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 240 100% Cache Stats: system.l1_cntrl0.L2cacheMemory system.l1_cntrl0.L2cacheMemory_total_misses: 510 @@ -289,9 +289,9 @@ O NC_DMA_GETS [0 ] 0 O Invalidate [0 ] 0 O Flush_line [0 ] 0 -M Load [131 ] 131 -M Ifetch [2337 ] 2337 -M Store [36 ] 36 +M Load [109 ] 109 +M Ifetch [2315 ] 2315 +M Store [35 ] 35 M L2_Replacement [344 ] 344 M L1_to_L2 [397 ] 397 M Trigger_L2_to_L1D [23 ] 23 @@ -304,9 +304,9 @@ M NC_DMA_GETS [0 ] 0 M Invalidate [0 ] 0 M Flush_line [0 ] 0 -MM Load [138 ] 138 +MM Load [124 ] 124 MM Ifetch [0 ] 0 -MM Store [211 ] 211 +MM Store [201 ] 201 MM L2_Replacement [81 ] 81 MM L1_to_L2 [105 ] 105 MM Trigger_L2_to_L1D [24 ] 24 @@ -319,6 +319,36 @@ MM NC_DMA_GETS [0 ] 0 MM Invalidate [0 ] 0 MM Flush_line [0 ] 0 +IR Load [0 ] 0 +IR Ifetch [0 ] 0 +IR Store [0 ] 0 +IR L1_to_L2 [0 ] 0 +IR Flush_line [0 ] 0 + +SR Load [0 ] 0 +SR Ifetch [0 ] 0 +SR Store [0 ] 0 +SR L1_to_L2 [0 ] 0 +SR Flush_line [0 ] 0 + +OR Load [0 ] 0 +OR Ifetch [0 ] 0 +OR Store [0 ] 0 +OR L1_to_L2 [0 ] 0 +OR Flush_line [0 ] 0 + +MR Load [22 ] 22 +MR Ifetch [22 ] 22 +MR Store [1 ] 1 +MR L1_to_L2 [0 ] 0 +MR Flush_line [0 ] 0 + +MMR Load [14 ] 14 +MMR Ifetch [0 ] 0 +MMR Store [10 ] 10 +MMR L1_to_L2 [0 ] 0 +MMR Flush_line [0 ] 0 + IM Load [0 ] 0 IM Ifetch [0 ] 0 IM Store [0 ] 0 @@ -468,13 +498,6 @@ IT Store [0 ] 0 IT L2_Replacement [0 ] 0 IT L1_to_L2 [0 ] 0 IT Complete_L2_to_L1 [0 ] 0 -IT Other_GETX [0 ] 0 -IT Other_GETS [0 ] 0 -IT Merged_GETS [0 ] 0 -IT Other_GETS_No_Mig [0 ] 0 -IT NC_DMA_GETS [0 ] 0 -IT Invalidate [0 ] 0 -IT Flush_line [0 ] 0 ST Load [0 ] 0 ST Ifetch [0 ] 0 @@ -482,13 +505,6 @@ ST Store [0 ] 0 ST L2_Replacement [0 ] 0 ST L1_to_L2 [0 ] 0 ST Complete_L2_to_L1 [0 ] 0 -ST Other_GETX [0 ] 0 -ST Other_GETS [0 ] 0 -ST Merged_GETS [0 ] 0 -ST Other_GETS_No_Mig [0 ] 0 -ST NC_DMA_GETS [0 ] 0 -ST Invalidate [0 ] 0 -ST Flush_line [0 ] 0 OT Load [0 ] 0 OT Ifetch [0 ] 0 @@ -496,13 +512,6 @@ OT Store [0 ] 0 OT L2_Replacement [0 ] 0 OT L1_to_L2 [0 ] 0 OT Complete_L2_to_L1 [0 ] 0 -OT Other_GETX [0 ] 0 -OT Other_GETS [0 ] 0 -OT Merged_GETS [0 ] 0 -OT Other_GETS_No_Mig [0 ] 0 -OT NC_DMA_GETS [0 ] 0 -OT Invalidate [0 ] 0 -OT Flush_line [0 ] 0 MT Load [0 ] 0 MT Ifetch [0 ] 0 @@ -510,13 +519,6 @@ MT Store [0 ] 0 MT L2_Replacement [0 ] 0 MT L1_to_L2 [0 ] 0 MT Complete_L2_to_L1 [45 ] 45 -MT Other_GETX [0 ] 0 -MT Other_GETS [0 ] 0 -MT Merged_GETS [0 ] 0 -MT Other_GETS_No_Mig [0 ] 0 -MT NC_DMA_GETS [0 ] 0 -MT Invalidate [0 ] 0 -MT Flush_line [0 ] 0 MMT Load [0 ] 0 MMT Ifetch [0 ] 0 @@ -524,13 +526,6 @@ MMT Store [0 ] 0 MMT L2_Replacement [0 ] 0 MMT L1_to_L2 [0 ] 0 MMT Complete_L2_to_L1 [24 ] 24 -MMT Other_GETX [0 ] 0 -MMT Other_GETS [0 ] 0 -MMT Merged_GETS [0 ] 0 -MMT Other_GETS_No_Mig [0 ] 0 -MMT NC_DMA_GETS [0 ] 0 -MMT Invalidate [0 ] 0 -MMT Flush_line [0 ] 0 MI_F Load [0 ] 0 MI_F Ifetch [0 ] 0 @@ -974,4 +969,5 @@ NO_F_W Pf_Replacement [0 ] 0 NO_F_W DMA_READ [0 ] 0 NO_F_W DMA_WRITE [0 ] 0 NO_F_W Memory_Data [0 ] 0 -NO_F_W GETF \ No newline at end of file +NO_F_W GETF [0 ] 0 + -- cgit v1.2.3