From 1b64bfa933745294667158d0ce22180780b2a22e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 7 Feb 2011 19:23:11 -0800 Subject: Stats: Back out broken update. --- .../ref/alpha/tru64/simple-timing/config.ini | 13 ++--------- .../00.hello/ref/alpha/tru64/simple-timing/simout | 12 +++++----- .../ref/alpha/tru64/simple-timing/stats.txt | 26 +++++----------------- 3 files changed, 14 insertions(+), 37 deletions(-) (limited to 'tests/quick/00.hello/ref/alpha/tru64/simple-timing') diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index f6e43920a..c142fa659 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -1,22 +1,13 @@ [root] type=Root children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 +dummy=0 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -166,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout index c6d73c335..6dd6e994b 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 6 2011 20:42:22 -M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates -M5 started Feb 6 2011 20:43:01 -M5 executing on SC2B0617 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:05 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 3dca8b0f4..f08ca087e 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 391701 # Simulator instruction rate (inst/s) -host_mem_usage 203856 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2449817385 # Simulator tick rate (ticks/s) +host_inst_rate 97740 # Simulator instruction rate (inst/s) +host_mem_usage 203308 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 629585132 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated @@ -226,24 +226,8 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 33538 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 33538 # Number of busy cycles -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- -- cgit v1.2.3