From a7e27f9a82300f213b268264e1dede222d26bd4d Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 22 Apr 2011 10:18:51 -0700 Subject: tests: updates for stat name change --- .../00.hello/ref/alpha/tru64/o3-timing/simout | 4 ++-- .../00.hello/ref/alpha/tru64/o3-timing/stats.txt | 28 +++++++++++----------- 2 files changed, 16 insertions(+), 16 deletions(-) (limited to 'tests/quick/00.hello/ref/alpha/tru64') diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index fc9118372..8a87312b4 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:04:56 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:15:23 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index e80a12bfa..b8b5c99cd 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 106844 # Simulator instruction rate (inst/s) -host_mem_usage 202600 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 323591910 # Simulator tick rate (ticks/s) +host_inst_rate 66320 # Simulator instruction rate (inst/s) +host_mem_usage 205872 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 201598879 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -251,16 +251,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 374 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 364 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 134 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 28 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 364 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 134 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 118 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -- cgit v1.2.3