From f125ef22b997d5ba6173d9d3f0d07ae741e279bd Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 19 Aug 2011 15:08:06 -0500 Subject: O3: Update stats for LSQ changes. --- .../00.hello/ref/alpha/tru64/o3-timing/simout | 6 +- .../00.hello/ref/alpha/tru64/o3-timing/stats.txt | 579 ++++++++++----------- 2 files changed, 292 insertions(+), 293 deletions(-) (limited to 'tests/quick/00.hello/ref/alpha/tru64') diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 74424d63b..b62422ecd 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:00:53 -gem5 started Jul 8 2011 15:21:09 +gem5 compiled Jul 15 2011 17:43:54 +gem5 started Jul 15 2011 20:04:15 gem5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 6921000 because target called exit() +Exiting @ tick 6833000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 5e52ef944..886aae88f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 6921000 # Number of ticks simulated +sim_ticks 6833000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33894 # Simulator instruction rate (inst/s) -host_tick_rate 98227338 # Simulator tick rate (ticks/s) -host_mem_usage 242788 # Number of bytes of host memory used +host_inst_rate 36521 # Simulator instruction rate (inst/s) +host_tick_rate 104491306 # Simulator tick rate (ticks/s) +host_mem_usage 242860 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 720 # DTB read hits -system.cpu.dtb.read_misses 34 # DTB read misses +system.cpu.dtb.read_hits 679 # DTB read hits +system.cpu.dtb.read_misses 26 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 754 # DTB read accesses -system.cpu.dtb.write_hits 354 # DTB write hits -system.cpu.dtb.write_misses 22 # DTB write misses +system.cpu.dtb.read_accesses 705 # DTB read accesses +system.cpu.dtb.write_hits 356 # DTB write hits +system.cpu.dtb.write_misses 18 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 376 # DTB write accesses -system.cpu.dtb.data_hits 1074 # DTB hits -system.cpu.dtb.data_misses 56 # DTB misses +system.cpu.dtb.write_accesses 374 # DTB write accesses +system.cpu.dtb.data_hits 1035 # DTB hits +system.cpu.dtb.data_misses 44 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1130 # DTB accesses -system.cpu.itb.fetch_hits 976 # ITB hits +system.cpu.dtb.data_accesses 1079 # DTB accesses +system.cpu.itb.fetch_hits 945 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1006 # ITB accesses +system.cpu.itb.fetch_accesses 975 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,245 +41,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 13843 # number of cpu cycles simulated +system.cpu.numCycles 13667 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1112 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 583 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 236 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 781 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 240 # Number of BTB hits +system.cpu.BPredUnit.lookups 1041 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 518 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 226 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 733 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 220 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 215 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 210 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3787 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6697 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1112 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 455 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1166 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 814 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 253 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 3751 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6413 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1041 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 430 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1115 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 754 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 212 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 781 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 976 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 159 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6557 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.021351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.437035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 945 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 157 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.004700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.420463 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5391 82.22% 82.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 67 1.02% 83.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 123 1.88% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 97 1.48% 86.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 146 2.23% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 50 0.76% 89.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 61 0.93% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 83 1.27% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 539 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5268 82.53% 82.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 60 0.94% 83.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 118 1.85% 85.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 94 1.47% 86.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 140 2.19% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 58 0.91% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 55 0.86% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 1.02% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 525 8.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6557 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080329 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.483782 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4673 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 269 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1132 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 476 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 152 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 6383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.076169 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.469232 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4642 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 226 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1083 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 426 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6020 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 5734 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 476 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4772 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 89 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 426 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4737 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 57 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1039 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 34 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5743 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 11 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4153 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6495 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6483 # Number of integer rename lookups +system.cpu.rename.RunCycles 997 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 19 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5480 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 14 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 3945 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6160 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6148 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2385 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2177 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 117 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 961 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 458 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. +system.cpu.rename.skidInsts 107 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 882 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4907 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 4659 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3996 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2355 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1385 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3882 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2129 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1179 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6557 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.609425 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.316967 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 6383 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.608178 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.298400 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 4952 75.52% 75.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 578 8.82% 84.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 360 5.49% 89.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 270 4.12% 93.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 209 3.19% 97.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 109 1.66% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 54 0.82% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17 0.26% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4812 75.39% 75.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 543 8.51% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 388 6.08% 89.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 264 4.14% 94.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 199 3.12% 97.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 107 1.68% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 55 0.86% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10 0.16% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6557 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6383 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 2.27% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 20 45.45% 47.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1 2.44% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 17 41.46% 43.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 56.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2819 70.55% 70.55% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 794 19.87% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 382 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2767 71.28% 71.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 734 18.91% 90.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 380 9.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3996 # Type of FU issued -system.cpu.iq.rate 0.288666 # Inst issue rate -system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011011 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14670 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7267 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3636 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3882 # Type of FU issued +system.cpu.iq.rate 0.284042 # Inst issue rate +system.cpu.iq.fu_busy_cnt 41 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010562 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14224 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6793 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3573 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4033 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3916 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 35 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 546 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 467 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 164 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 476 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 79 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5242 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 961 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 458 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 426 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 44 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5003 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 64 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 882 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 137 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 189 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3843 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 755 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 153 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 121 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 175 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3749 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 706 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 133 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 329 # number of nop insts executed -system.cpu.iew.exec_refs 1131 # number of memory reference insts executed -system.cpu.iew.exec_branches 644 # Number of branches executed -system.cpu.iew.exec_stores 376 # Number of stores executed -system.cpu.iew.exec_rate 0.277613 # Inst execution rate -system.cpu.iew.wb_sent 3725 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3642 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1733 # num instructions producing a value -system.cpu.iew.wb_consumers 2231 # num instructions consuming a value +system.cpu.iew.exec_nop 338 # number of nop insts executed +system.cpu.iew.exec_refs 1080 # number of memory reference insts executed +system.cpu.iew.exec_branches 629 # Number of branches executed +system.cpu.iew.exec_stores 374 # Number of stores executed +system.cpu.iew.exec_rate 0.274310 # Inst execution rate +system.cpu.iew.wb_sent 3647 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3579 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1702 # num instructions producing a value +system.cpu.iew.wb_consumers 2165 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.263093 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.776782 # average fanout of values written-back +system.cpu.iew.wb_rate 0.261872 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 2657 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2418 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 159 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6081 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.423615 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.271187 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 5957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.432432 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.291215 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5177 85.13% 85.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 230 3.78% 88.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 323 5.31% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 118 1.94% 96.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 67 1.10% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 52 0.86% 98.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 37 0.61% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.33% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 57 0.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5066 85.04% 85.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 221 3.71% 88.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 314 5.27% 94.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 118 1.98% 96.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 71 1.19% 97.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 53 0.89% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 34 0.57% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.34% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 60 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 5957 # Number of insts commited each cycle system.cpu.commit.count 2576 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 709 # Number of memory references committed @@ -289,49 +288,49 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 57 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11010 # The number of ROB reads -system.cpu.rob.rob_writes 10947 # The number of ROB writes +system.cpu.rob.rob_reads 10644 # The number of ROB reads +system.cpu.rob.rob_writes 10417 # The number of ROB writes system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7286 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.799330 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.799330 # CPI: Total CPI of All Threads -system.cpu.ipc 0.172434 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.172434 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4649 # number of integer regfile reads -system.cpu.int_regfile_writes 2817 # number of integer regfile writes +system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads +system.cpu.ipc 0.174654 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.174654 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4520 # number of integer regfile reads +system.cpu.int_regfile_writes 2768 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 92.452549 # Cycle average of tags in use -system.cpu.icache.total_refs 735 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 91.574139 # Cycle average of tags in use +system.cpu.icache.total_refs 704 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.972973 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.805405 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 92.452549 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.045143 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 735 # number of ReadReq hits -system.cpu.icache.demand_hits 735 # number of demand (read+write) hits -system.cpu.icache.overall_hits 735 # number of overall hits +system.cpu.icache.occ_blocks::0 91.574139 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.044714 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 704 # number of ReadReq hits +system.cpu.icache.demand_hits 704 # number of demand (read+write) hits +system.cpu.icache.overall_hits 704 # number of overall hits system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses system.cpu.icache.demand_misses 241 # number of demand (read+write) misses system.cpu.icache.overall_misses 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 8775500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 8775500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 8775500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 976 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 976 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 976 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.246926 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.246926 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.246926 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36412.863071 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36412.863071 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36412.863071 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 8777500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 8777500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 8777500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 945 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 945 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 945 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.255026 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.255026 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.255026 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36421.161826 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36421.161826 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36421.161826 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -348,52 +347,52 @@ system.cpu.icache.ReadReq_mshr_misses 185 # nu system.cpu.icache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 185 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 6554000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 6554000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 6554000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 6554500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 6554500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 6554500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.189549 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.189549 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.189549 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35427.027027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35427.027027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35427.027027 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.195767 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.195767 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.195767 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35429.729730 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.779373 # Cycle average of tags in use -system.cpu.dcache.total_refs 794 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.439198 # Cycle average of tags in use +system.cpu.dcache.total_refs 765 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.341176 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 45.779373 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.011177 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 572 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 45.439198 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.011094 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 543 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits -system.cpu.dcache.demand_hits 794 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 794 # number of overall hits -system.cpu.dcache.ReadReq_misses 116 # number of ReadReq misses +system.cpu.dcache.demand_hits 765 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 765 # number of overall hits +system.cpu.dcache.ReadReq_misses 101 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses -system.cpu.dcache.demand_misses 188 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 188 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3872000 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 173 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3605000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 2816500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 6688500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 6688500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 6421500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 6421500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 644 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 982 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 982 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.168605 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 938 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 938 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.156832 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.191446 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.191446 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33379.310345 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate 0.184435 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.184435 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35693.069307 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 39118.055556 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35577.127660 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35577.127660 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 37118.497110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 37118.497110 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -403,50 +402,50 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 103 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 88 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 88 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2165500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2169000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 872000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3037500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3037500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3041000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3041000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.088663 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.094720 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.086558 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.086558 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35500 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.090618 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.090618 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35557.377049 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35735.294118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35735.294118 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 121.331762 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 120.203882 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 121.331762 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.003703 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 120.203882 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.003668 # Average percentage of cache occupancy system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 270 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 8443500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 8447500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 831000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 9274500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 9274500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency 9278500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 9278500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses @@ -455,10 +454,10 @@ system.cpu.l2cache.ReadReq_miss_rate 1 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34323.170732 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34339.430894 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34625 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34350 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34350 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34364.814815 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34364.814815 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,19 +474,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 24 # nu system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7659500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 7661500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 8415500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 8415500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8417500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8417500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.178862 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.308943 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31168.518519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31168.518519 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31175.925926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31175.925926 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -- cgit v1.2.3