From ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Thu, 25 Feb 2010 10:08:41 -0800 Subject: stats: update stats for the changes I pushed re: shared cache occupancy --- .../00.hello/ref/alpha/linux/inorder-timing/config.ini | 5 ++++- tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout | 8 ++++---- .../00.hello/ref/alpha/linux/inorder-timing/stats.txt | 14 ++++++++++---- tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini | 8 ++++---- tests/quick/00.hello/ref/alpha/linux/o3-timing/simout | 10 +++++----- tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt | 14 ++++++++++---- .../00.hello/ref/alpha/linux/simple-atomic/config.ini | 2 +- tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout | 8 ++++---- .../quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt | 8 ++++---- .../00.hello/ref/alpha/linux/simple-timing/config.ini | 8 ++++---- tests/quick/00.hello/ref/alpha/linux/simple-timing/simout | 8 ++++---- .../quick/00.hello/ref/alpha/linux/simple-timing/stats.txt | 14 ++++++++++---- tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini | 8 ++++---- tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr | 2 +- tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout | 8 ++++---- tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 14 ++++++++++---- .../00.hello/ref/alpha/tru64/simple-atomic/config.ini | 2 +- tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr | 2 +- tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout | 8 ++++---- .../quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt | 8 ++++---- .../00.hello/ref/alpha/tru64/simple-timing/config.ini | 8 ++++---- tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr | 2 +- tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout | 8 ++++---- .../quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt | 14 ++++++++++---- 24 files changed, 112 insertions(+), 79 deletions(-) (limited to 'tests/quick/00.hello/ref/alpha') diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini index 5ab5381fc..24854ed7e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -79,6 +79,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -113,6 +114,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -147,6 +149,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -188,7 +191,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 4ad6292c5..c9e5e8882 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 29 2010 09:13:03 -M5 revision 23ae96d82d21+ 6704+ default qtip tip inorder_hello_alpha -M5 started Jan 29 2010 09:13:04 -M5 executing on zooks +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:21:00 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index b9a12afbb..77487dead 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 23048 # Simulator instruction rate (inst/s) -host_mem_usage 153228 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host -host_tick_rate 112412599 # Simulator tick rate (ticks/s) +host_inst_rate 37021 # Simulator instruction rate (inst/s) +host_mem_usage 190468 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 180549624 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000031 # Number of seconds simulated @@ -72,6 +72,8 @@ system.cpu.dcache.demand_mshr_misses 182 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.025315 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 103.689640 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56217.032967 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53217.032967 # average overall mshr miss latency @@ -143,6 +145,8 @@ system.cpu.icache.demand_mshr_misses 285 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.063659 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 130.373495 # Average occupied blocks per context system.cpu.icache.overall_accesses 7277 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55521.594684 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency @@ -234,6 +238,8 @@ system.cpu.l2cache.demand_mshr_misses 452 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.005540 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 181.532273 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52069.690265 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 39956.858407 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 9978c29e9..1b5a762f3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -281,7 +281,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -316,7 +316,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 207a844c8..0bdde157a 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:03:45 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:06 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing +M5 compiled Feb 24 2010 23:12:54 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 01:04:08 +M5 executing on SC2B0619 +command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 584bdfccf..7fffd3b0b 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 76035 # Simulator instruction rate (inst/s) -host_mem_usage 189864 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 148017846 # Simulator tick rate (ticks/s) +host_inst_rate 104903 # Simulator instruction rate (inst/s) +host_mem_usage 190976 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 203948336 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -93,6 +93,8 @@ system.cpu.dcache.demand_mshr_misses 188 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.026922 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 110.270477 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency @@ -199,6 +201,8 @@ system.cpu.icache.demand_mshr_misses 307 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.077417 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 158.550695 # Average occupied blocks per context system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency @@ -387,6 +391,8 @@ system.cpu.l2cache.demand_mshr_misses 480 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.006558 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 214.901533 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index adc37d29a..a69256420 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout index 52c0469fb..0053084d5 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:57:23 -M5 executing on zizzer +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:01:37 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 3077042e9..301281a5e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 272186 # Simulator instruction rate (inst/s) -host_mem_usage 192556 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 135226078 # Simulator tick rate (ticks/s) +host_inst_rate 1228467 # Simulator instruction rate (inst/s) +host_mem_usage 182556 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 587751371 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index c0449a709..9b07b770c 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout index 9f3354a73..7ee1b22c1 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:26 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:17:21 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:20:02 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt index fcff4ad2a..998b710c1 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 244055 # Simulator instruction rate (inst/s) -host_mem_usage 201804 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 1274748085 # Simulator tick rate (ticks/s) +host_inst_rate 605866 # Simulator instruction rate (inst/s) +host_mem_usage 190120 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 3109075847 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000034 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 182 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.025418 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 104.111261 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses 279 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.062817 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 128.649737 # Average occupied blocks per context system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency @@ -207,6 +211,8 @@ system.cpu.l2cache.demand_mshr_misses 446 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.005491 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 179.928092 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index f6582aa5c..c164849b4 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -281,7 +281,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -316,7 +316,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr index bb8489f81..67f69f09d 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 8a4be24f4..703e5cb77 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:03:45 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:07 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:44:06 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 9712e8b8d..48416d4fa 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 18690 # Simulator instruction rate (inst/s) -host_mem_usage 188768 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 56136046 # Simulator tick rate (ticks/s) +host_inst_rate 86395 # Simulator instruction rate (inst/s) +host_mem_usage 189960 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 257307637 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -93,6 +93,8 @@ system.cpu.dcache.demand_mshr_misses 98 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.011202 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 45.884316 # Average occupied blocks per context system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency @@ -199,6 +201,8 @@ system.cpu.icache.demand_mshr_misses 181 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.043324 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 88.727286 # Average occupied blocks per context system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency @@ -386,6 +390,8 @@ system.cpu.l2cache.demand_mshr_misses 266 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.003380 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 110.762790 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 255dbd855..c65c23354 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr index bb8489f81..67f69f09d 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout index 0cca599d2..870c07405 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:39:03 -M5 executing on zizzer +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:37:14 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 8610ea2cd..eeba7561c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 312515 # Simulator instruction rate (inst/s) -host_mem_usage 191632 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 151541696 # Simulator tick rate (ticks/s) +host_inst_rate 794145 # Simulator instruction rate (inst/s) +host_mem_usage 181656 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host +host_tick_rate 371138444 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index b2b4a540c..f316dec65 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr index bb8489f81..67f69f09d 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout index 103381b7c..2135491a6 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:26 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:17:22 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:11:06 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 72ee5d06d..3c63125e0 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 89461 # Simulator instruction rate (inst/s) -host_mem_usage 200972 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 597928210 # Simulator tick rate (ticks/s) +host_inst_rate 400715 # Simulator instruction rate (inst/s) +host_mem_usage 189300 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 2582342449 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 93 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.011615 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 47.575114 # Average occupied blocks per context system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses 163 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.039276 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 80.437325 # Average occupied blocks per context system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -206,6 +210,8 @@ system.cpu.l2cache.demand_mshr_misses 245 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.003139 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 102.857609 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -- cgit v1.2.3