From a17dbdf8834b84f05a8f5154a74ac819fe8adc7c Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 25 Jan 2012 17:19:50 +0000
Subject: stats: Update stats for final tick and memory bandwidth patches

---
 .../ref/mips/linux/simple-timing-ruby/config.ini    | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

(limited to 'tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini')

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 41938cc87..e5b4b16c8 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -7,9 +7,10 @@ time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
 mem_mode=timing
 memories=system.physmem
+num_work_ids=16
 physmem=system.physmem
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -136,6 +138,7 @@ version=0
 [system.l1_cntrl0.cacheMemory]
 type=RubyCache
 assoc=2
+is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
 size=256
@@ -164,11 +167,11 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.l1_cntrl0.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=network profiler tracer
+children=network profiler
 block_size_bytes=64
 clock=1
 mem_size=134217728
@@ -252,8 +255,14 @@ hot_lines=false
 num_of_sequencers=1
 ruby_system=system.ruby
 
-[system.ruby.tracer]
-type=RubyTracer
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
 ruby_system=system.ruby
-warmup_length=100000
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[1]
+port=system.system_port
 
-- 
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