From e63c73b45d688c7af7a1a3ed01dbde538c57acc2 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 13 May 2010 23:45:59 -0400 Subject: BPRED: Update regressions for tournament predictor fix. --- .../00.hello/ref/mips/linux/inorder-timing/simout | 8 +- .../ref/mips/linux/inorder-timing/stats.txt | 8 +- .../00.hello/ref/mips/linux/o3-timing/config.ini | 2 +- .../quick/00.hello/ref/mips/linux/o3-timing/simout | 10 +- .../00.hello/ref/mips/linux/o3-timing/stats.txt | 384 ++++++++++----------- 5 files changed, 206 insertions(+), 206 deletions(-) (limited to 'tests/quick/00.hello/ref/mips/linux') diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index aa3193437..12732e5e1 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 23 2010 00:25:27 -M5 revision ba1ff0a71710+ 7040+ default tip -M5 started Mar 23 2010 00:25:28 -M5 executing on zooks +M5 compiled May 12 2010 02:40:58 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:41:01 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 6c70d7ee8..76dc624e3 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 30626 # Simulator instruction rate (inst/s) -host_mem_usage 154136 # Number of bytes of host memory used +host_inst_rate 30301 # Simulator instruction rate (inst/s) +host_mem_usage 205096 # Number of bytes of host memory used host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 153245779 # Simulator tick rate (ticks/s) +host_tick_rate 151651964 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated sim_ticks 29206500 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 2090 # Number of Instructions Requests that completed in this resource. system.cpu.Branch-Predictor.BTBHits 0 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 641 # Number of BTB lookups +system.cpu.Branch-Predictor.BTBLookups 499 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.Branch-Predictor.condIncorrect 666 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 677 # Number of conditional branches predicted diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index a93b6565a..a56ef0667 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -412,7 +412,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index f2820f9aa..0c4704bfb 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:11:23 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:40:58 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:41:01 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 14060500 because target called exit() +Exiting @ tick 14021500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index e79cbdaa4..ab93396d9 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 82851 # Simulator instruction rate (inst/s) -host_mem_usage 191760 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 224354167 # Simulator tick rate (ticks/s) +host_inst_rate 60574 # Simulator instruction rate (inst/s) +host_mem_usage 205208 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 163793003 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14060500 # Number of ticks simulated +sim_ticks 14021500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 572 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1960 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 546 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1900 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 751 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1593 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2416 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 404 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 747 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1589 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2405 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 400 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 916 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 65 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 69 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 14561 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.400110 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.121131 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 14488 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.402126 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.127822 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 11999 82.41% 82.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 1213 8.33% 90.74% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 529 3.63% 94.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 291 2.00% 96.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 294 2.02% 98.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 71 0.49% 98.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 62 0.43% 99.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 37 0.25% 99.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 65 0.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 11934 82.37% 82.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1210 8.35% 90.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 523 3.61% 94.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 292 2.02% 96.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 294 2.03% 98.38% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 67 0.46% 98.84% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 62 0.43% 99.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 37 0.26% 99.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 69 0.48% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 14561 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 14488 # Number of insts commited each cycle system.cpu.commit.COM:count 5826 # Number of instructions committed system.cpu.commit.COM:loads 1164 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2089 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 620 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 616 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 6017 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5972 # The number of squashed insts skipped by commit system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 5.440511 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.440511 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2321 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34074.626866 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36043.956044 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2187 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4566000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.057734 # miss rate for ReadReq accesses +system.cpu.cpi 5.425421 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.425421 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2310 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34156.716418 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36032.967033 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2176 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4577000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.058009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3280000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.039207 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 3279000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.039394 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27570.707071 # average WriteReq miss latency @@ -73,56 +73,56 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # m system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.226950 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.148936 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3246 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29592.807425 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2815 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12754500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.132779 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 3235 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29618.329466 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2804 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 12765500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.133230 # miss rate for demand accesses system.cpu.dcache.demand_misses 431 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 276 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5587000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.047751 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 5586000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.047913 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.022292 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 91.308954 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 3246 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29592.807425 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.022304 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 91.357241 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 3235 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29618.329466 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2815 # number of overall hits -system.cpu.dcache.overall_miss_latency 12754500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.132779 # miss rate for overall accesses +system.cpu.dcache.overall_hits 2804 # number of overall hits +system.cpu.dcache.overall_miss_latency 12765500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.133230 # miss rate for overall accesses system.cpu.dcache.overall_misses 431 # number of overall misses system.cpu.dcache.overall_mshr_hits 276 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.047751 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 5586000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.047913 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 91.308954 # Cycle average of tags in use -system.cpu.dcache.total_refs 2852 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.357241 # Cycle average of tags in use +system.cpu.dcache.total_refs 2841 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 519 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 139 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 139 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 14436 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 10077 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3965 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1080 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 521 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 138 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 14337 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 10064 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3903 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1073 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 267 # Number of squashed instructions handled by decode system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits @@ -133,151 +133,151 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2416 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2220 # Number of cache lines fetched -system.cpu.fetch.Cycles 6371 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 355 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 15622 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 767 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.085911 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2220 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.555508 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15641 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.998785 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.252974 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2405 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2216 # Number of cache lines fetched +system.cpu.fetch.Cycles 6303 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 358 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 15547 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 763 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.085758 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2216 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 946 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.554379 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 15561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.999100 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.261901 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 11507 73.57% 73.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1847 11.81% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 223 1.43% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 141 0.90% 87.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 312 1.99% 89.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 120 0.77% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 308 1.97% 92.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 254 1.62% 94.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 929 5.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 11491 73.84% 73.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1812 11.64% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 195 1.25% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 140 0.90% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 320 2.06% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 114 0.73% 90.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 289 1.86% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 259 1.66% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 941 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15641 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 2220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35681.279621 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34902.735562 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1798 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15057500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.190090 # miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 15561 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 2216 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35687.203791 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34908.814590 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1794 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15060000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.190433 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 422 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 93 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11483000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.148198 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 11485000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.148466 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.465046 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.452888 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2220 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35681.279621 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency -system.cpu.icache.demand_hits 1798 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15057500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.190090 # miss rate for demand accesses +system.cpu.icache.demand_accesses 2216 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35687.203791 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency +system.cpu.icache.demand_hits 1794 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15060000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.190433 # miss rate for demand accesses system.cpu.icache.demand_misses 422 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 93 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11483000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.148198 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 11485000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.148466 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.076179 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 156.015053 # Average occupied blocks per context -system.cpu.icache.overall_accesses 2220 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35681.279621 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.076241 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 156.140617 # Average occupied blocks per context +system.cpu.icache.overall_accesses 2216 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35687.203791 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1798 # number of overall hits -system.cpu.icache.overall_miss_latency 15057500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.190090 # miss rate for overall accesses +system.cpu.icache.overall_hits 1794 # number of overall hits +system.cpu.icache.overall_miss_latency 15060000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.190433 # miss rate for overall accesses system.cpu.icache.overall_misses 422 # number of overall misses system.cpu.icache.overall_mshr_hits 93 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11483000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.148198 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 11485000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.148466 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 16 # number of replacements system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 156.015053 # Cycle average of tags in use -system.cpu.icache.total_refs 1798 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 156.140617 # Cycle average of tags in use +system.cpu.icache.total_refs 1794 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12481 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1253 # Number of branches executed -system.cpu.iew.EXEC:nop 1830 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.295249 # Inst execution rate -system.cpu.iew.EXEC:refs 3456 # number of memory reference insts executed +system.cpu.idleCycles 12483 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1268 # Number of branches executed +system.cpu.iew.EXEC:nop 1827 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.295643 # Inst execution rate +system.cpu.iew.EXEC:refs 3444 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1049 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 4132 # num instructions consuming a value -system.cpu.iew.WB:count 7536 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.703291 # average fanout of values written-back +system.cpu.iew.WB:consumers 4139 # num instructions consuming a value +system.cpu.iew.WB:count 7538 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.704035 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 2906 # num instructions producing a value -system.cpu.iew.WB:rate 0.267975 # insts written-back per cycle -system.cpu.iew.WB:sent 7618 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 681 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 2914 # num instructions producing a value +system.cpu.iew.WB:rate 0.268792 # insts written-back per cycle +system.cpu.iew.WB:sent 7625 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 679 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2806 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2797 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 963 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 953 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11847 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2407 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 549 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8303 # Number of executed instructions +system.cpu.iew.iewDispatchedInsts 11802 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2395 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 544 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8291 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1080 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1073 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1642 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1633 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 272 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 409 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.183806 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.183806 # IPC: Total IPC of All Threads +system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 395 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.184318 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.184318 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5184 58.56% 58.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2595 29.32% 87.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1064 12.02% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5173 58.55% 58.55% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.63% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2589 29.30% 87.96% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1064 12.04% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8852 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 8835 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018301 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.018336 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 8 4.94% 4.94% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.94% # attempts to use FU when none available @@ -292,31 +292,31 @@ system.cpu.iq.ISSUE:fu_full::MemRead 100 61.73% 66.67% # at system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 15641 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.565948 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.209939 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 15561 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567766 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217819 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 11653 74.50% 74.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1757 11.23% 85.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 814 5.20% 90.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 738 4.72% 95.66% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 342 2.19% 97.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 199 1.27% 99.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.58% 99.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 32 0.20% 99.90% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 11605 74.58% 74.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1745 11.21% 85.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 791 5.08% 90.87% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 727 4.67% 95.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 340 2.18% 97.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 213 1.37% 99.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 93 0.60% 99.70% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 32 0.21% 99.90% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 15641 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.314771 # Inst issue rate -system.cpu.iq.iqInstsAdded 10005 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8852 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 15561 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.315041 # Inst issue rate +system.cpu.iq.iqInstsAdded 9963 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8835 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4214 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 36 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2725 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2680 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -337,12 +337,12 @@ system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 420 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.221154 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31133.413462 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.990476 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12953500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12951500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990476 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) @@ -364,30 +364,30 @@ system.cpu.l2cache.blocked_cycles::no_targets 0 system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34356.223176 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 16010000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.991489 # miss rate for demand accesses system.cpu.l2cache.demand_misses 466 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 14521500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 14519500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.991489 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 466 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006413 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 210.151573 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006418 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 210.308968 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34356.223176 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits system.cpu.l2cache.overall_miss_latency 16010000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.991489 # miss rate for overall accesses system.cpu.l2cache.overall_misses 466 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 14521500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14519500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.991489 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 466 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -395,27 +395,27 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 402 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 210.151573 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 210.308968 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2806 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2797 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 28122 # number of cpu cycles simulated +system.cpu.numCycles 28044 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 5 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 10468 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 10455 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 9 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15900 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 13681 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8420 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3575 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1080 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 15765 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 13587 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8333 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3513 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1073 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 19 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 5010 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 494 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:UndoneMaps 4923 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 496 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 17 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 111 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed -- cgit v1.2.3