From 9e45ada1718b6df9310757fdc7cd78db4695516f Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 9 Sep 2010 14:40:19 -0400 Subject: stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU. --- .../00.hello/ref/power/linux/o3-timing/simerr | 2 +- .../00.hello/ref/power/linux/o3-timing/simout | 14 +- .../00.hello/ref/power/linux/o3-timing/stats.txt | 293 ++++++++++----------- 3 files changed, 150 insertions(+), 159 deletions(-) (limited to 'tests/quick/00.hello/ref/power') diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index 91e0a0356..d552956c6 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 17982776. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 16785032. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index b9932c144..f838ffb8f 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing/simout -Redirecting stderr to build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing/simerr +Redirecting stdout to build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing/simout +Redirecting stderr to build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +7,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:59:10 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:59:12 +M5 compiled Aug 26 2010 12:59:22 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:59:25 M5 executing on zizzer -command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing +command line: build/POWER_SE/m5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11864500 because target called exit() +Exiting @ tick 11733000 because target called exit() diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index e78679f83..914654ad0 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 82571 # Simulator instruction rate (inst/s) -host_mem_usage 202992 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 168278845 # Simulator tick rate (ticks/s) +host_inst_rate 8561 # Simulator instruction rate (inst/s) +host_mem_usage 202624 # Number of bytes of host memory used +host_seconds 0.68 # Real time elapsed on the host +host_tick_rate 17311106 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11864500 # Number of ticks simulated +sim_ticks 11733000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBHits 687 # Number of BTB hits system.cpu.BPredUnit.BTBLookups 1888 # Number of BTB lookups @@ -19,23 +19,23 @@ system.cpu.BPredUnit.usedRAS 189 # Nu system.cpu.commit.COM:branches 1038 # Number of branches committed system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 10785 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.537784 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.251292 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 10473 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.553805 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.272090 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 8225 76.26% 76.26% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1129 10.47% 86.73% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 673 6.24% 92.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 258 2.39% 95.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 226 2.10% 97.46% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 120 1.11% 98.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 82 0.76% 99.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 21 0.19% 99.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 51 0.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 7930 75.72% 75.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1118 10.68% 86.39% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 663 6.33% 92.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 256 2.44% 95.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 224 2.14% 97.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 123 1.17% 98.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 87 0.83% 99.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 21 0.20% 99.51% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 51 0.49% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 10785 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 10473 # Number of insts commited each cycle system.cpu.commit.COM:count 5800 # Number of instructions committed system.cpu.commit.COM:loads 962 # Number of loads committed system.cpu.commit.COM:membars 7 # Number of memory barriers committed @@ -47,30 +47,30 @@ system.cpu.commit.commitNonSpecStalls 16 # Th system.cpu.commit.commitSquashedInsts 3389 # The number of squashed insts skipped by commit system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 4.091379 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.091379 # CPI: Total CPI of All Threads +system.cpu.cpi 4.046034 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.046034 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1444 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33612.359551 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 33681.818182 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34464.285714 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1355 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2991500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.061634 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_hits 1356 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2964000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.060942 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 32 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 1930000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.038781 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33542.735043 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36053.846154 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 695 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 11773500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.335564 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 351 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 286 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2343500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.062141 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 65 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 33737.864078 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36302.083333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 737 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 10425000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.295411 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 309 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 261 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1742500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 20.125000 # Average number of references to valid blocks. @@ -80,51 +80,51 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2490 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33556.818182 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2050 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 14765000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.176707 # miss rate for demand accesses -system.cpu.dcache.demand_misses 440 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4273500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.048594 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 121 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_avg_miss_latency 33725.440806 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2093 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 13389000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.159438 # miss rate for demand accesses +system.cpu.dcache.demand_misses 397 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 293 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3672500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.041767 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 104 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.016240 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 66.517345 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.016245 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 66.538229 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2490 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33556.818182 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 33725.440806 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2050 # number of overall hits -system.cpu.dcache.overall_miss_latency 14765000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.176707 # miss rate for overall accesses -system.cpu.dcache.overall_misses 440 # number of overall misses -system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4273500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.048594 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 121 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2093 # number of overall hits +system.cpu.dcache.overall_miss_latency 13389000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.159438 # miss rate for overall accesses +system.cpu.dcache.overall_misses 397 # number of overall misses +system.cpu.dcache.overall_mshr_hits 293 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3672500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.041767 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 104 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 66.517345 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 66.538229 # Cycle average of tags in use system.cpu.dcache.total_refs 2093 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1153 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 885 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 150 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 267 # Number of times decode resolved a branch system.cpu.decode.DECODE:DecodedInsts 10406 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7618 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1941 # Number of cycles decode is running +system.cpu.decode.DECODE:IdleCycles 7574 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1944 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 570 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 416 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.decode.DECODE:UnblockCycles 70 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -140,36 +140,36 @@ system.cpu.fetch.Cycles 3561 # Nu system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.088496 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.089487 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 876 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.492499 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 11355 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.029238 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.423250 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rate 0.498018 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 11043 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.058317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.450976 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9285 81.77% 81.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 161 1.42% 83.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 189 1.66% 84.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 155 1.37% 86.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 202 1.78% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 136 1.20% 89.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 272 2.40% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 77 0.68% 92.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 878 7.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8973 81.26% 81.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 161 1.46% 82.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 189 1.71% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 155 1.40% 85.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 202 1.83% 87.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 136 1.23% 88.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 272 2.46% 91.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 77 0.70% 92.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 878 7.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11355 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 11043 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36423.575130 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34778.614458 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36422.279793 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34777.108434 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1104 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14059500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 14059000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.259060 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 386 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11546500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11546000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.222819 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -181,31 +181,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1490 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36423.575130 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 36422.279793 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34777.108434 # average overall mshr miss latency system.cpu.icache.demand_hits 1104 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14059500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 14059000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.259060 # miss rate for demand accesses system.cpu.icache.demand_misses 386 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11546500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11546000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.222819 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.078771 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 161.323458 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.078715 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 161.207549 # Average occupied blocks per context system.cpu.icache.overall_accesses 1490 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36423.575130 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 36422.279793 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34777.108434 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1104 # number of overall hits -system.cpu.icache.overall_miss_latency 14059500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 14059000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.259060 # miss rate for overall accesses system.cpu.icache.overall_misses 386 # number of overall misses system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11546500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11546000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.222819 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -213,27 +213,27 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 161.323458 # Cycle average of tags in use +system.cpu.icache.tagsinuse 161.207549 # Cycle average of tags in use system.cpu.icache.total_refs 1104 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 12424 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 1261 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.328319 # Inst execution rate +system.cpu.iew.EXEC:rate 0.331998 # Inst execution rate system.cpu.iew.EXEC:refs 2813 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1315 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5889 # num instructions consuming a value +system.cpu.iew.WB:consumers 5926 # num instructions consuming a value system.cpu.iew.WB:count 7582 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.646290 # average fanout of values written-back +system.cpu.iew.WB:fanout 0.645461 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3806 # num instructions producing a value -system.cpu.iew.WB:rate 0.319511 # insts written-back per cycle +system.cpu.iew.WB:producers 3825 # num instructions producing a value +system.cpu.iew.WB:rate 0.323092 # insts written-back per cycle system.cpu.iew.WB:sent 7642 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 277 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 117 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 130 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 1681 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch @@ -246,7 +246,7 @@ system.cpu.iew.iewIQFullEvents 4 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 570 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking +system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores @@ -260,8 +260,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 404 # system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.244416 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.244416 # IPC: Total IPC of All Threads +system.cpu.ipc 0.247156 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.247156 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntAlu 5126 63.37% 63.37% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued @@ -293,24 +293,24 @@ system.cpu.iq.ISSUE:fu_full::MemRead 73 47.71% 54.90% # at system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.10% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 11355 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.712373 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.391316 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 11043 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.732500 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.410424 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8066 71.03% 71.03% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1182 10.41% 81.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 820 7.22% 88.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 507 4.46% 93.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 388 3.42% 96.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 218 1.92% 98.47% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 121 1.07% 99.53% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 46 0.41% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 7773 70.39% 70.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1167 10.57% 80.96% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 813 7.36% 88.32% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 500 4.53% 92.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 391 3.54% 96.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 222 2.01% 98.40% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 124 1.12% 99.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 46 0.42% 99.94% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 7 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 11355 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.340877 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 11043 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.344697 # Inst issue rate system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ @@ -328,46 +328,37 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34927.083333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31750 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1676500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34947.916667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31770.833333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1677500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1524000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1525000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 388 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34327.631579 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31150 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34326.315789 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31147.368421 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 13044500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 13044000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.979381 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 380 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11837000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 11836000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979381 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 380 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34264.705882 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31176.470588 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 582500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.022039 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.021053 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34394.859813 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34396.028037 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14721000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 14721500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.981651 # miss rate for demand accesses system.cpu.l2cache.demand_misses 428 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -377,14 +368,14 @@ system.cpu.l2cache.demand_mshr_misses 428 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005582 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 182.925254 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005863 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 192.111326 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34394.859813 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34396.028037 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14721000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 14721500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.981651 # miss rate for overall accesses system.cpu.l2cache.overall_misses 428 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -394,9 +385,9 @@ system.cpu.l2cache.overall_mshr_misses 428 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 363 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 380 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 182.925254 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 192.111326 # Cycle average of tags in use system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks @@ -404,24 +395,24 @@ system.cpu.memDep0.conflictingLoads 67 # Nu system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 23730 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 323 # Number of cycles rename is blocking +system.cpu.numCycles 23467 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 312 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 7801 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 213 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IdleCycles 7756 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 194 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:RenameLookups 16232 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 9925 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 8708 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1823 # Number of cycles rename is running +system.cpu.rename.RENAME:RunCycles 1825 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 263 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UnblockCycles 243 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 575 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializeStallCycles 337 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 494 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 473 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 9 # Number of system calls ---------- End Simulation Statistics ---------- -- cgit v1.2.3