From ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Thu, 25 Feb 2010 10:08:41 -0800 Subject: stats: update stats for the changes I pushed re: shared cache occupancy --- .../quick/00.hello/ref/x86/linux/simple-atomic/config.ini | 2 +- tests/quick/00.hello/ref/x86/linux/simple-atomic/simout | 8 ++++---- tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt | 8 ++++---- .../quick/00.hello/ref/x86/linux/simple-timing/config.ini | 8 ++++---- tests/quick/00.hello/ref/x86/linux/simple-timing/simout | 8 ++++---- tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt | 14 ++++++++++---- 6 files changed, 27 insertions(+), 21 deletions(-) (limited to 'tests/quick/00.hello/ref/x86') diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index 911046b97..49018d812 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -57,7 +57,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 0030aae6b..d7f9758f3 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 8 2009 12:09:45 -M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch -M5 started Aug 8 2009 12:09:46 -M5 executing on tater +M5 compiled Feb 25 2010 03:41:05 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 04:11:29 +M5 executing on SC2B0619 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index a72432b3a..8b2e120b0 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 23019 # Simulator instruction rate (inst/s) -host_mem_usage 193704 # Number of bytes of host memory used -host_seconds 0.41 # Real time elapsed on the host -host_tick_rate 13302912 # Simulator tick rate (ticks/s) +host_inst_rate 940985 # Simulator instruction rate (inst/s) +host_mem_usage 185436 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 530148334 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9519 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini index 5db260ab9..64e4a7561 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 299195d5b..de395dbab 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 8 2009 12:09:45 -M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch -M5 started Aug 8 2009 12:09:46 -M5 executing on tater +M5 compiled Feb 25 2010 03:41:05 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 04:11:30 +M5 executing on SC2B0619 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index e83d6fcbe..a1830d00b 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 21415 # Simulator instruction rate (inst/s) -host_mem_usage 201336 # Number of bytes of host memory used -host_seconds 0.44 # Real time elapsed on the host -host_tick_rate 66853602 # Simulator tick rate (ticks/s) +host_inst_rate 605496 # Simulator instruction rate (inst/s) +host_mem_usage 193040 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1857026858 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9519 # Number of instructions simulated sim_seconds 0.000030 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 152 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.019744 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 80.872189 # Average occupied blocks per context system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses 228 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.052069 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 106.638328 # Average occupied blocks per context system.cpu.icache.overall_accesses 6887 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency @@ -175,6 +179,8 @@ system.cpu.l2cache.demand_mshr_misses 360 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.003910 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 128.120518 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -- cgit v1.2.3