From 9b67f3723e48efdd0a0b640ff82cfcf8aad3a659 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 18 Jan 2011 16:30:06 -0600 Subject: Stats: Update stats for previous set of patches. --- tests/quick/00.hello/ref/alpha/linux/o3-timing/simout | 6 +++--- tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt | 11 ++++++----- tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout | 6 +++--- tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 9 +++++---- tests/quick/00.hello/ref/mips/linux/o3-timing/simout | 6 +++--- tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 9 +++++---- tests/quick/00.hello/ref/power/linux/o3-timing/simerr | 2 +- tests/quick/00.hello/ref/power/linux/o3-timing/simout | 6 +++--- tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt | 11 ++++++----- 9 files changed, 35 insertions(+), 31 deletions(-) (limited to 'tests/quick/00.hello/ref') diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index c56e2a305..7b6a1125b 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 13:43:59 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:24:57 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 70e07c2b3..72be64488 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 34451 # Simulator instruction rate (inst/s) -host_mem_usage 203748 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 66857161 # Simulator tick rate (ticks/s) +host_inst_rate 10121 # Simulator instruction rate (inst/s) +host_mem_usage 203516 # Number of bytes of host memory used +host_seconds 0.63 # Real time elapsed on the host +host_tick_rate 19665204 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -143,9 +143,10 @@ system.cpu.dtb.write_hits 1051 # DT system.cpu.dtb.write_misses 25 # DTB write misses system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 1774 # Number of cache lines fetched -system.cpu.fetch.Cycles 4193 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2385 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 13186 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 503 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.089503 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1774 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 62d772708..fe2af5e09 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 13:43:59 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:48:46 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index c55fb3eb0..2363f1511 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 60581 # Simulator instruction rate (inst/s) -host_mem_usage 202656 # Number of bytes of host memory used +host_inst_rate 61982 # Simulator instruction rate (inst/s) +host_mem_usage 202420 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 184013511 # Simulator tick rate (ticks/s) +host_tick_rate 188319059 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -143,9 +143,10 @@ system.cpu.dtb.write_hits 351 # DT system.cpu.dtb.write_misses 17 # DTB write misses system.cpu.fetch.Branches 926 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 782 # Number of cache lines fetched -system.cpu.fetch.Cycles 1799 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 988 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 5752 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 249 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.063420 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 782 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index ac792f6c6..6b2281542 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 14 2010 23:58:18 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 14 2010 23:58:34 +M5 compiled Jan 17 2011 21:17:36 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 21:17:39 M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 8e9b6a4ca..a5f35787b 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 72923 # Simulator instruction rate (inst/s) +host_inst_rate 35741 # Simulator instruction rate (inst/s) host_mem_usage 204488 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 179666090 # Simulator tick rate (ticks/s) +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 88262097 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000013 # Number of seconds simulated @@ -136,9 +136,10 @@ system.cpu.dtb.write_hits 0 # DT system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.fetch.Branches 1744 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 1555 # Number of cache lines fetched -system.cpu.fetch.Cycles 4407 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2837 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 11052 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 393 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.068205 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1555 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index 1fe8a27f7..29a71f392 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 17040520. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 16206088. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index d3bc761bb..6bd581433 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 00:01:15 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 00:01:17 +M5 compiled Jan 17 2011 17:18:01 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 17:18:03 M5 executing on zizzer command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index 6f780bef0..8b311d8d3 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 15746 # Simulator instruction rate (inst/s) -host_mem_usage 202164 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host -host_tick_rate 31829526 # Simulator tick rate (ticks/s) +host_inst_rate 12762 # Simulator instruction rate (inst/s) +host_mem_usage 202140 # Number of bytes of host memory used +host_seconds 0.45 # Real time elapsed on the host +host_tick_rate 25804848 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -136,9 +136,10 @@ system.cpu.dtb.write_hits 0 # DT system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.fetch.Branches 2100 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 1490 # Number of cache lines fetched -system.cpu.fetch.Cycles 3561 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2070 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.089487 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss -- cgit v1.2.3