From a51e2fd8bd581d45f8a87874c9a6680f99d11e24 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 26 Aug 2007 20:27:53 -0700
Subject: Stats: Update the stats.

--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
---
 .../01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini     | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

(limited to 'tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini')

diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 5a35877e6..71b1480ab 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus tracer workload0 workload1
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload0 workload1
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -36,6 +36,7 @@ decodeToRenameDelay=1
 decodeWidth=8
 defer_registration=false
 dispatchWidth=8
+dtb=system.cpu.dtb
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -53,6 +54,7 @@ iewToRenameDelay=1
 instShiftAmt=2
 issueToExecuteDelay=1
 issueWidth=8
+itb=system.cpu.itb
 localCtrBits=2
 localHistoryBits=11
 localHistoryTableSize=2048
@@ -130,6 +132,10 @@ write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
+[system.cpu.dtb]
+type=AlphaDTB
+size=64
+
 [system.cpu.fuPool]
 type=FUPool
 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
@@ -303,6 +309,10 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.itb]
+type=AlphaITB
+size=48
+
 [system.cpu.l2cache]
 type=BaseCache
 addr_range=0:18446744073709551615
-- 
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