From 9493501fdb087c82111d8692995474f2e8f3f390 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Fri, 10 Aug 2007 16:14:02 -0400
Subject: Regression: Add an I/O Cache to the full system regressions that have
 a cache.

--HG--
extra : convert_revision : 8ba96e21be2f602eed8258d410038dbe998ef176
---
 .../linux/tsunami-simple-atomic-dual/config.ini    | 66 ++++++++++++++++++----
 1 file changed, 56 insertions(+), 10 deletions(-)

(limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini')

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index d3a9862e8..1f7fcb065 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -5,7 +5,7 @@ dummy=0
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
+children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 console=/dist/m5/system/binaries/console
@@ -22,8 +22,8 @@ system_type=34
 [system.bridge]
 type=Bridge
 delay=50000
-fix_partial_write_a=false
-fix_partial_write_b=true
+filter_ranges_a=0:18446744073709551615
+filter_ranges_b=0:8589934591
 nack_delay=4000
 req_size_a=16
 req_size_b=16
@@ -65,10 +65,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -103,10 +105,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -171,10 +175,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -209,10 +215,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -295,17 +303,55 @@ clock=1000
 responder_set=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+cpu_side_filter_ranges=549755813888:18446744073709551615
+hash_delay=1
+latency=50000
+lifo=false
+max_miss_count=0
+mem_side_filter_ranges=0:18446744073709551615
+mshrs=20
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+split=false
+split_size=0
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[2]
 
 [system.l2c]
 type=BaseCache
 addr_range=0:18446744073709551615
 assoc=8
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=10000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=92
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -329,7 +375,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[2]
+mem_side=system.membus.port[3]
 
 [system.membus]
 type=Bus
@@ -340,7 +386,7 @@ clock=1000
 responder_set=false
 width=64
 default=system.membus.responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
+port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.responder]
 type=IsaFake
@@ -474,8 +520,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[28]
-dma=system.iobus.port[29]
+config=system.iobus.port[29]
+dma=system.iobus.port[30]
 pio=system.iobus.port[27]
 
 [system.tsunami.ethernet.configdata]
@@ -840,8 +886,8 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
+config=system.iobus.port[31]
+dma=system.iobus.port[32]
 pio=system.iobus.port[26]
 
 [system.tsunami.ide.configdata]
-- 
cgit v1.2.3