From a17dbdf8834b84f05a8f5154a74ac819fe8adc7c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 25 Jan 2012 17:19:50 +0000 Subject: stats: Update stats for final tick and memory bandwidth patches --- .../alpha/linux/tsunami-simple-atomic/stats.txt | 965 +++++++++++---------- 1 file changed, 488 insertions(+), 477 deletions(-) (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt') diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 85848a462..7f4c99b34 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,236 +1,267 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4724073 # Simulator instruction rate (inst/s) -host_mem_usage 291084 # Number of bytes of host memory used -host_seconds 12.71 # Real time elapsed on the host -host_tick_rate 143937379014 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated sim_ticks 1829332258000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::0 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 17162 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses::0 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits::0 7807782 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate::0 0.180671 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1721705 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses -system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 199282 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits::0 5848212 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate::0 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 304362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15682061 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13655994 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.129196 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 2026067 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 511.997802 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses::0 15682061 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13655994 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13655994 # number of overall hits -system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.129196 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 2026067 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2026067 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2042700 # number of replacements -system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 825183 # number of writebacks -system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_hits 16062925 # DTB hits -system.cpu.dtb.data_misses 11471 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv +final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 3300922 # Simulator instruction rate (inst/s) +host_tick_rate 100577077281 # Simulator tick rate (ticks/s) +host_mem_usage 294216 # Number of bytes of host memory used +host_seconds 18.19 # Real time elapsed on the host +sim_insts 60038305 # Number of instructions simulated +system.physmem.bytes_read 71650816 # Number of bytes read from this memory +system.physmem.bytes_inst_read 955904 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10156864 # Number of bytes written to this memory +system.physmem.num_reads 1119544 # Number of read requests responded to by this memory +system.physmem.num_writes 158701 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 39167743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 522543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5552225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 44719968 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 1045877 # number of replacements +system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use +system.l2c.total_refs 2291835 # Total number of references to valid blocks. +system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.126306 # Average number of references to valid blocks. +system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 10193.605493 # Average occupied blocks per context +system.l2c.occ_blocks::1 23613.410409 # Average occupied blocks per context +system.l2c.occ_percent::0 0.155542 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.360312 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1699395 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits +system.l2c.Writeback_hits::0 825291 # number of Writeback hits +system.l2c.Writeback_hits::total 825291 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 1 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 185383 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits +system.l2c.demand_hits::0 1884778 # number of demand (read+write) hits +system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits +system.l2c.overall_hits::0 1884778 # number of overall hits +system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::total 1884778 # number of overall hits +system.l2c.ReadReq_misses::0 959629 # number of ReadReq misses +system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 12 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 118859 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 118859 # number of ReadExReq misses +system.l2c.demand_misses::0 1078488 # number of demand (read+write) misses +system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 1078488 # number of demand (read+write) misses +system.l2c.overall_misses::0 1078488 # number of overall misses +system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::total 1078488 # number of overall misses +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2659024 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2659024 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 825291 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 825291 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 13 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 304242 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2963266 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2963266 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2963266 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.360895 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.923077 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.390673 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.363952 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.363952 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency +system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 no_value # average overall miss latency +system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks 117189 # number of writebacks +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.replacements 41686 # number of replacements +system.iocache.tagsinuse 1.225570 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 1.225570 # Average occupied blocks per context +system.iocache.occ_percent::1 0.076598 # Average percentage of cache occupancy +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.ReadReq_misses::1 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 0 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks 41512 # number of writebacks +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 0 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.read_acv 210 # DTB read access violations +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 9710427 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.write_acv 157 # DTB write access violations +system.cpu.dtb.read_acv 210 # DTB read access violations +system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.write_hits 6352498 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits::0 59129922 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate::0 0.015324 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 920221 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 60050143 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.demand_hits::0 59129922 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.015324 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 920221 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 511.215243 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.998467 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses::0 60050143 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 59129922 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 59129922 # number of overall hits -system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.015324 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 920221 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 920221 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 919594 # number of replacements -system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use -system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 108 # number of writebacks -system.cpu.idle_fraction 0.983585 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 4979654 # ITB accesses -system.cpu.itb.fetch_acv 184 # ITB acv +system.cpu.dtb.write_acv 157 # DTB write access violations +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 16062925 # DTB hits +system.cpu.dtb.data_misses 11471 # DTB misses +system.cpu.dtb.data_acv 367 # DTB access violations +system.cpu.dtb.data_accesses 1020787 # DTB accesses system.cpu.itb.fetch_hits 4974648 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.fetch_acv 184 # ITB acv +system.cpu.itb.fetch_accesses 4979654 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed -system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed -system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192180 # number of callpals executed +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.numCycles 3658664408 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 60038305 # Number of instructions executed +system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1484182 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913521 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 16115709 # number of memory refs +system.cpu.num_load_insts 9747513 # Number of load instructions +system.cpu.num_store_insts 6368196 # Number of store instructions +system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles +system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles +system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983585 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl @@ -250,20 +281,6 @@ system.cpu.kern.ipl_used::0 0.981732 # fr system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1738 -system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.402439 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -277,261 +294,255 @@ system.cpu.kern.syscall::23 4 1.23% 37.12% # nu system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed -system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed -system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed -system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed -system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed -system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed -system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed -system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed -system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed -system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed -system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed -system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed -system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed -system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed -system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed -system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed -system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed -system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed -system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles -system.cpu.numCycles 3658664408 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles -system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles -system.cpu.num_insts 60038305 # Number of instructions executed -system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses -system.cpu.num_int_insts 55913521 # number of integer instructions -system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written -system.cpu.num_load_insts 9747513 # Number of load instructions -system.cpu.num_mem_refs 16115709 # number of memory refs -system.cpu.num_store_insts 6368196 # Number of store instructions -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_blocks::1 1.225570 # Average occupied blocks per context -system.iocache.occ_percent::1 0.076598 # Average percentage of cache occupancy -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 41686 # number of replacements -system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.225570 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 304242 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_hits::0 185383 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits -system.l2c.ReadExReq_miss_rate::0 0.390673 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 118859 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 118859 # number of ReadExReq misses -system.l2c.ReadReq_accesses::0 2659024 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2659024 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 1699395 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.360895 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 959629 # number of ReadReq misses -system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 13 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_hits::0 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_rate::0 0.923077 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 12 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.l2c.Writeback_accesses::0 825291 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 825291 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 825291 # number of Writeback hits -system.l2c.Writeback_hits::total 825291 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 2.126306 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2963266 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2963266 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency -system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 1884778 # number of demand (read+write) hits -system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.363952 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 1078488 # number of demand (read+write) misses -system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 1078488 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 10193.605493 # Average occupied blocks per context -system.l2c.occ_blocks::1 23613.410409 # Average occupied blocks per context -system.l2c.occ_percent::0 0.155542 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.360312 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 2963266 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 no_value # average overall miss latency -system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1884778 # number of overall hits -system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1884778 # number of overall hits -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.363952 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses -system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 1078488 # number of overall misses -system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 1078488 # number of overall misses -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 1045877 # number of replacements -system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use -system.l2c.total_refs 2291835 # Total number of references to valid blocks. -system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 117189 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post +system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed +system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed +system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed +system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed +system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed +system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed +system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed +system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed +system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed +system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed +system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed +system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed +system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed +system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed +system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed +system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed +system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed +system.cpu.kern.syscall::total 326 # number of syscalls executed +system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed +system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed +system.cpu.kern.callpal::total 192180 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_good::idle 171 +system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.402439 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.cpu.icache.replacements 919594 # number of replacements +system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use +system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 511.215243 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.998467 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 59129922 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits +system.cpu.icache.demand_hits::0 59129922 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 59129922 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 59129922 # number of overall hits +system.cpu.icache.ReadReq_misses::0 920221 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses +system.cpu.icache.demand_misses::0 920221 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 920221 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 920221 # number of overall misses +system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 60050143 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 60050143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.015324 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.015324 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::0 0.015324 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 108 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2042700 # number of replacements +system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use +system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 511.997802 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 5848212 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 199282 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 13655994 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 13655994 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 13655994 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1721705 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 304362 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::0 2026067 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 2026067 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 2026067 # number of overall misses +system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15682061 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15682061 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::0 0.129196 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::0 0.129196 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 825183 # number of writebacks +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- -- cgit v1.2.3