From 7b40c36fbd1c348e5ef43231325923aae1cd0809 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@gmail.com>
Date: Wed, 22 Apr 2009 01:55:52 -0400
Subject: Update stats for new single bad-address responder. Mostly just
 config.ini updates, though the different response latency for bad addresses
 caused very minor timing changes in the O3 Linux boot tests.

---
 .../alpha/linux/tsunami-simple-timing/config.ini   | 40 +++++-----------------
 1 file changed, 9 insertions(+), 31 deletions(-)

(limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini')

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index a7d96b196..64bcede47 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -66,11 +66,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=1000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=4
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -102,11 +101,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=1000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=4
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -196,14 +194,13 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst
 
 [system.iocache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_range=0:8589934591
 assoc=8
 block_size=64
-cpu_side_filter_ranges=549755813888:18446744073709551615
+forward_snoops=false
 hash_delay=1
 latency=50000
 max_miss_count=0
-mem_side_filter_ranges=0:18446744073709551615
 mshrs=20
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -231,11 +228,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=8
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=10000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=92
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -260,20 +256,20 @@ mem_side=system.membus.port[3]
 
 [system.membus]
 type=Bus
-children=responder
+children=badaddr_responder
 block_size=64
 bus_id=1
 clock=1000
 header_cycles=1
 responder_set=false
 width=64
-default=system.membus.responder.pio
+default=system.membus.badaddr_responder.pio
 port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
 
-[system.membus.responder]
+[system.membus.badaddr_responder]
 type=IsaFake
 pio_addr=0
-pio_latency=1
+pio_latency=1000
 pio_size=8
 platform=system.tsunami
 ret_bad_addr=true
@@ -316,32 +312,14 @@ port=3456
 
 [system.toL2Bus]
 type=Bus
-children=responder
 block_size=64
 bus_id=0
 clock=1000
 header_cycles=1
 responder_set=false
 width=64
-default=system.toL2Bus.responder.pio
 port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
-[system.toL2Bus.responder]
-type=IsaFake
-pio_addr=0
-pio_latency=1
-pio_size=8
-platform=system.tsunami
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.toL2Bus.default
-
 [system.tsunami]
 type=Tsunami
 children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
-- 
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