From ddd179a4189d6f51f7be81567e1119aa67533dae Mon Sep 17 00:00:00 2001
From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Thu, 6 Nov 2008 11:11:42 -0500
Subject: Reference updates.  Since split cache is gone, a lot of config.ini
 changes, and minor changes to stats that are likely due to the decoupling of
 insertions/evictions in the cache.

---
 .../ref/alpha/linux/tsunami-simple-timing/config.ini   | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

(limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini')

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index c6c4209f5..3e8e04375 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -35,7 +35,7 @@ side_b=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
 clock=500
 cpu_id=0
 defer_registration=false
@@ -45,6 +45,7 @@ do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -67,7 +68,6 @@ block_size=64
 cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
-lifo=false
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
@@ -85,8 +85,6 @@ prefetcher_size=100
 prioritizeRequests=false
 repl=Null
 size=32768
-split=false
-split_size=0
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -107,7 +105,6 @@ block_size=64
 cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
-lifo=false
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=4
@@ -125,8 +122,6 @@ prefetcher_size=100
 prioritizeRequests=false
 repl=Null
 size=32768
-split=false
-split_size=0
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -135,6 +130,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.toL2Bus.port[1]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaITB
 size=48
@@ -203,7 +201,6 @@ block_size=64
 cpu_side_filter_ranges=549755813888:18446744073709551615
 hash_delay=1
 latency=50000
-lifo=false
 max_miss_count=0
 mem_side_filter_ranges=0:18446744073709551615
 mshrs=20
@@ -221,8 +218,6 @@ prefetcher_size=100
 prioritizeRequests=false
 repl=Null
 size=1024
-split=false
-split_size=0
 subblock_size=0
 tgts_per_mshr=12
 trace_addr=0
@@ -239,7 +234,6 @@ block_size=64
 cpu_side_filter_ranges=
 hash_delay=1
 latency=10000
-lifo=false
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=92
@@ -257,8 +251,6 @@ prefetcher_size=100
 prioritizeRequests=false
 repl=Null
 size=4194304
-split=false
-split_size=0
 subblock_size=0
 tgts_per_mshr=16
 trace_addr=0
-- 
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