From ddd179a4189d6f51f7be81567e1119aa67533dae Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Thu, 6 Nov 2008 11:11:42 -0500 Subject: Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache. --- .../ref/alpha/linux/tsunami-simple-timing/config.ini | 18 +++++------------- .../ref/alpha/linux/tsunami-simple-timing/m5stats.txt | 8 ++++---- .../ref/alpha/linux/tsunami-simple-timing/stderr | 2 +- .../ref/alpha/linux/tsunami-simple-timing/stdout | 11 ++++++----- 4 files changed, 16 insertions(+), 23 deletions(-) (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing') diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index c6c4209f5..3e8e04375 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -35,7 +35,7 @@ side_b=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb tracer +children=dcache dtb icache interrupts itb tracer clock=500 cpu_id=0 defer_registration=false @@ -45,6 +45,7 @@ do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -67,7 +68,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -85,8 +85,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -107,7 +105,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=1000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=4 @@ -125,8 +122,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=32768 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -135,6 +130,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.toL2Bus.port[1] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaITB size=48 @@ -203,7 +201,6 @@ block_size=64 cpu_side_filter_ranges=549755813888:18446744073709551615 hash_delay=1 latency=50000 -lifo=false max_miss_count=0 mem_side_filter_ranges=0:18446744073709551615 mshrs=20 @@ -221,8 +218,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=1024 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=12 trace_addr=0 @@ -239,7 +234,6 @@ block_size=64 cpu_side_filter_ranges= hash_delay=1 latency=10000 -lifo=false max_miss_count=0 mem_side_filter_ranges= mshrs=92 @@ -257,8 +251,6 @@ prefetcher_size=100 prioritizeRequests=false repl=Null size=4194304 -split=false -split_size=0 subblock_size=0 tgts_per_mshr=16 trace_addr=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 7b835d1b3..5185f8b73 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1555255 # Simulator instruction rate (inst/s) -host_mem_usage 285892 # Number of bytes of host memory used -host_seconds 36.11 # Real time elapsed on the host -host_tick_rate 53447376481 # Simulator tick rate (ticks/s) +host_inst_rate 1640475 # Simulator instruction rate (inst/s) +host_mem_usage 286536 # Number of bytes of host memory used +host_seconds 34.24 # Real time elapsed on the host +host_tick_rate 56375976626 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56165112 # Number of instructions simulated sim_seconds 1.930166 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 45392f539..1a557daf8 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,4 +1,4 @@ warn: kernel located at: /dist/m5/system/binaries/vmlinux warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: Entering event queue @ 0. Starting simulation... +warn: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 6ec325f9b..5cef637b5 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 27 2008 21:08:15 -M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083 -M5 commit date Sat Sep 27 21:03:50 2008 -0700 -M5 started Sep 27 2008 21:08:17 -M5 executing on piton +M5 compiled Nov 5 2008 22:27:11 +M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 +M5 commit date Wed Nov 05 16:19:17 2008 -0500 +M5 started Nov 5 2008 22:27:38 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1930165791000 because m5_exit instruction encountered -- cgit v1.2.3