From 9e45ada1718b6df9310757fdc7cd78db4695516f Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 9 Sep 2010 14:40:19 -0400 Subject: stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU. --- .../ref/alpha/eio/simple-timing/config.ini | 2 +- .../ref/alpha/eio/simple-timing/simout | 12 +-- .../ref/alpha/eio/simple-timing/stats.txt | 85 ++++++++++------------ 3 files changed, 45 insertions(+), 54 deletions(-) (limited to 'tests/quick/20.eio-short/ref/alpha/eio') diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index f8aa4e39a..380aa38da 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -153,7 +153,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout index 3a00a516f..2cf640280 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:33:34 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing +M5 compiled Aug 26 2010 19:15:13 +M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix +M5 started Aug 26 2010 19:20:56 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... main dictionary has 1245 entries 49508 bytes wasted ->Exiting @ tick 737389000 because a thread reached the max instruction count +>Exiting @ tick 727929000 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index fb5a17baa..43dab4e5c 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1409192 # Simulator instruction rate (inst/s) -host_mem_usage 189184 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host -host_tick_rate 2076450214 # Simulator tick rate (ticks/s) +host_inst_rate 1184343 # Simulator instruction rate (inst/s) +host_mem_usage 203180 # Number of bytes of host memory used +host_seconds 0.42 # Real time elapsed on the host +host_tick_rate 1723169900 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated -sim_seconds 0.000737 # Number of seconds simulated -sim_ticks 737389000 # Number of ticks simulated +sim_seconds 0.000728 # Number of seconds simulated +sim_ticks 727929000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 315 # nu system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 56029 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17416000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16483000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7784000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 7367000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. @@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 180149 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 35056000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003463 # miss rate for demand accesses -system.cpu.dcache.demand_misses 626 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 25424000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses +system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 33178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003463 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 626 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 24062000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.069937 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 286.463742 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.070111 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 287.175167 # Average occupied blocks per context system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 180149 # number of overall hits -system.cpu.dcache.overall_miss_latency 35056000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses -system.cpu.dcache.overall_misses 626 # number of overall misses +system.cpu.dcache.overall_hits 180321 # number of overall hits +system.cpu.dcache.overall_miss_latency 25424000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses +system.cpu.dcache.overall_misses 454 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 33178000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003463 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 24062000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 286.463742 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 287.175167 # Cycle average of tags in use system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 403 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.129067 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 264.328816 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.129371 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 264.952126 # Average occupied blocks per context system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 264.328816 # Cycle average of tags in use +system.cpu.icache.tagsinuse 264.952126 # Cycle average of tags in use system.cpu.icache.total_refs 499617 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -179,15 +179,6 @@ system.cpu.l2cache.ReadReq_misses 718 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 172 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 8944000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 172 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6880000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 172 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -210,8 +201,8 @@ system.cpu.l2cache.demand_mshr_misses 857 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.011298 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 370.220381 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.014692 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 481.419470 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -227,14 +218,14 @@ system.cpu.l2cache.overall_mshr_misses 857 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 370.220381 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 481.419470 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1474778 # number of cpu cycles simulated +system.cpu.numCycles 1455858 # number of cpu cycles simulated system.cpu.num_insts 500001 # Number of instructions executed system.cpu.num_refs 182222 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls -- cgit v1.2.3