From bb3f7dc83b9a4c7b20aeb893fea447854c855225 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Fri, 3 Aug 2007 18:04:30 -0400 Subject: tests: new ref outputs for new cache model --HG-- extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6 --- .../50.memtest/ref/alpha/linux/memtest/config.ini | 102 ++------------------- 1 file changed, 9 insertions(+), 93 deletions(-) (limited to 'tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini') diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index e30600052..8bac0dec4 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -27,12 +27,9 @@ test=system.cpu0.l1c.cpu_side [system.cpu0.l1c] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -50,12 +47,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu0.l1c.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -64,11 +59,6 @@ write_buffers=8 cpu_side=system.cpu0.test mem_side=system.toL2Bus.port[1] -[system.cpu0.l1c.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu1] type=MemTest children=l1c @@ -87,12 +77,9 @@ test=system.cpu1.l1c.cpu_side [system.cpu1.l1c] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -110,12 +97,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu1.l1c.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -124,11 +109,6 @@ write_buffers=8 cpu_side=system.cpu1.test mem_side=system.toL2Bus.port[2] -[system.cpu1.l1c.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu2] type=MemTest children=l1c @@ -147,12 +127,9 @@ test=system.cpu2.l1c.cpu_side [system.cpu2.l1c] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -170,12 +147,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu2.l1c.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -184,11 +159,6 @@ write_buffers=8 cpu_side=system.cpu2.test mem_side=system.toL2Bus.port[3] -[system.cpu2.l1c.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu3] type=MemTest children=l1c @@ -207,12 +177,9 @@ test=system.cpu3.l1c.cpu_side [system.cpu3.l1c] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -230,12 +197,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu3.l1c.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -244,11 +209,6 @@ write_buffers=8 cpu_side=system.cpu3.test mem_side=system.toL2Bus.port[4] -[system.cpu3.l1c.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu4] type=MemTest children=l1c @@ -267,12 +227,9 @@ test=system.cpu4.l1c.cpu_side [system.cpu4.l1c] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -290,12 +247,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu4.l1c.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -304,11 +259,6 @@ write_buffers=8 cpu_side=system.cpu4.test mem_side=system.toL2Bus.port[5] -[system.cpu4.l1c.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu5] type=MemTest children=l1c @@ -327,12 +277,9 @@ test=system.cpu5.l1c.cpu_side [system.cpu5.l1c] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -350,12 +297,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu5.l1c.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -364,11 +309,6 @@ write_buffers=8 cpu_side=system.cpu5.test mem_side=system.toL2Bus.port[6] -[system.cpu5.l1c.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu6] type=MemTest children=l1c @@ -387,12 +327,9 @@ test=system.cpu6.l1c.cpu_side [system.cpu6.l1c] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -410,12 +347,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu6.l1c.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -424,11 +359,6 @@ write_buffers=8 cpu_side=system.cpu6.test mem_side=system.toL2Bus.port[7] -[system.cpu6.l1c.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.cpu7] type=MemTest children=l1c @@ -447,12 +377,9 @@ test=system.cpu7.l1c.cpu_side [system.cpu7.l1c] type=BaseCache -children=protocol -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=4 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=1000 lifo=false @@ -470,12 +397,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=system.cpu7.l1c.protocol repl=Null size=32768 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=8 trace_addr=0 @@ -484,11 +409,6 @@ write_buffers=8 cpu_side=system.cpu7.test mem_side=system.toL2Bus.port[8] -[system.cpu7.l1c.protocol] -type=CoherenceProtocol -do_upgrades=true -protocol=moesi - [system.funcmem] type=PhysicalMemory file= @@ -499,11 +419,9 @@ port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system [system.l2c] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=8 block_size=64 -compressed_bus=false -compression_latency=0 hash_delay=1 latency=10000 lifo=false @@ -521,12 +439,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=65536 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=16 trace_addr=0 -- cgit v1.2.3