From 7b40c36fbd1c348e5ef43231325923aae1cd0809 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 22 Apr 2009 01:55:52 -0400 Subject: Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests. --- .../50.memtest/ref/alpha/linux/memtest/config.ini | 27 ++++++++-------------- .../50.memtest/ref/alpha/linux/memtest/simout | 8 +++---- .../50.memtest/ref/alpha/linux/memtest/stats.txt | 6 ++--- 3 files changed, 16 insertions(+), 25 deletions(-) (limited to 'tests/quick/50.memtest') diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index f9dfac7de..bb5089d27 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -30,11 +30,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -78,11 +77,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -126,11 +124,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -174,11 +171,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -222,11 +218,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -270,11 +265,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -318,11 +312,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -366,11 +359,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=12 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -408,11 +400,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=92 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout index 84934c75f..0a2232d19 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:34:30 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 17:07:10 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt index 2fa4194ff..451bddd68 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 328212 # Number of bytes of host memory used -host_seconds 135.65 # Real time elapsed on the host -host_tick_rate 1982429 # Simulator tick rate (ticks/s) +host_mem_usage 326608 # Number of bytes of host memory used +host_seconds 197.86 # Real time elapsed on the host +host_tick_rate 1359114 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000269 # Number of seconds simulated sim_ticks 268915439 # Number of ticks simulated -- cgit v1.2.3