From 1efe42fa97ed03662666cafee1b9dec9dfe524e9 Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Sat, 11 Oct 2014 16:18:51 -0500
Subject: stats: updates due to changes to x86, stale configs.

---
 .../linux/tsunami-simple-timing-dual/config.ini    | 43 ++++++++++++++++++++--
 1 file changed, 40 insertions(+), 3 deletions(-)

(limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual')

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 39f3dd971..f7c4e30f8 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -379,7 +379,7 @@ eventq_index=0
 sys=system
 
 [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
 header_cycles=1
@@ -460,11 +460,12 @@ sequential_access=false
 size=4194304
 
 [system.membus]
-type=CoherentBus
+type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
 header_cycles=1
+snoop_filter=Null
 system=system
 use_default_range=false
 width=8
@@ -492,8 +493,33 @@ pio=system.membus.default
 
 [system.physmem]
 type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
 activation_limit=4
 addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
 channels=1
@@ -502,6 +528,7 @@ conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+dll=true
 eventq_index=0
 in_addr_map=true
 max_accesses_per_row=16
@@ -515,19 +542,26 @@ read_buffer_size=32
 static_backend_latency=10000
 static_frontend_latency=10000
 tBURST=5000
+tCCD_L=0
 tCK=1250
 tCL=13750
+tCS=2500
 tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=260000
 tRP=13750
 tRRD=6000
+tRRD_L=0
 tRTP=7500
 tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
 write_low_thresh_perc=50
@@ -555,10 +589,11 @@ output=true
 port=3456
 
 [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 header_cycles=1
+snoop_filter=Null
 system=system
 use_default_range=false
 width=8
@@ -627,6 +662,7 @@ HeaderType=0
 InterruptLine=30
 InterruptPin=1
 LatencyTimer=0
+LegacyIOBase=0
 MSICAPBaseOffset=0
 MSICAPCapId=0
 MSICAPMaskBits=0
@@ -1082,6 +1118,7 @@ HeaderType=0
 InterruptLine=31
 InterruptPin=1
 LatencyTimer=0
+LegacyIOBase=0
 MSICAPBaseOffset=0
 MSICAPCapId=0
 MSICAPMaskBits=0
-- 
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