From 93c0307d418e08db609818f19f5d2b02d45e7465 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 29 Oct 2014 23:18:29 -0500 Subject: tests: Update regressions for the new kernels and various preceeding fixes. --- .../alpha/linux/tsunami-simple-timing-dual/config.ini | 15 ++++++++------- .../ref/alpha/linux/tsunami-simple-timing-dual/simerr | 1 + .../ref/alpha/linux/tsunami-simple-timing-dual/simout | 10 +++++----- .../alpha/linux/tsunami-simple-timing-dual/stats.txt | 18 +++++++----------- 4 files changed, 21 insertions(+), 23 deletions(-) (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual') diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index f7c4e30f8..8f2902a1b 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -26,8 +26,8 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/dist/binaries/ts_osfpal +readfile=/work/gem5.latest/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -339,7 +339,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -362,7 +362,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -527,6 +527,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 @@ -577,7 +578,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr index 20fe2d682..518507880 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr @@ -1,3 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 2d1ba2c03..537e9e8af 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 17:25:12 +gem5 compiled Oct 29 2014 09:12:51 +gem5 started Oct 29 2014 09:20:02 gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 688618000 -Exiting @ tick 1960909874500 because m5_exit instruction encountered +info: Launching CPU 1 @ 690168000 +Exiting @ tick 1961826628500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index f259fe3aa..dd52d45d1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.961827 # Nu sim_ticks 1961826628500 # Number of ticks simulated final_tick 1961826628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 855480 # Simulator instruction rate (inst/s) -host_op_rate 855480 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27561784483 # Simulator tick rate (ticks/s) -host_mem_usage 318220 # Number of bytes of host memory used -host_seconds 71.18 # Real time elapsed on the host +host_inst_rate 1248737 # Simulator instruction rate (inst/s) +host_op_rate 1248737 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40231703865 # Simulator tick rate (ticks/s) +host_mem_usage 312404 # Number of bytes of host memory used +host_seconds 48.76 # Real time elapsed on the host sim_insts 60892387 # Number of instructions simulated sim_ops 60892387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -728,8 +728,6 @@ system.iocache.fast_writes 41552 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses @@ -744,16 +742,14 @@ system.iocache.overall_mshr_miss_latency::tsunami.ide 12199383 system.iocache.overall_mshr_miss_latency::total 12199383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60199.384049 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60199.384049 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency -- cgit v1.2.3