From 8b4b1dcb86b0799a8c32056427581a8b6249a3bf Mon Sep 17 00:00:00 2001 From: Andreas Hansson <andreas.hansson@arm.com> Date: Sun, 23 Mar 2014 11:12:19 -0400 Subject: stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller. --- .../linux/tsunami-simple-timing-dual/stats.txt | 2548 ++++++++++---------- .../alpha/linux/tsunami-simple-timing/stats.txt | 1538 ++++++------ 2 files changed, 1956 insertions(+), 2130 deletions(-) (limited to 'tests/quick/fs/10.linux-boot/ref/alpha') diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 14efebcaa..85845c2fe 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.960910 # Number of seconds simulated -sim_ticks 1960909874500 # Number of ticks simulated -final_tick 1960909874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.961814 # Number of seconds simulated +sim_ticks 1961813569500 # Number of ticks simulated +final_tick 1961813569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1305982 # Simulator instruction rate (inst/s) -host_op_rate 1305981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42027651646 # Simulator tick rate (ticks/s) -host_mem_usage 309852 # Number of bytes of host memory used -host_seconds 46.66 # Real time elapsed on the host -sim_insts 60933947 # Number of instructions simulated -sim_ops 60933947 # Number of ops (including micro ops) simulated +host_inst_rate 1769979 # Simulator instruction rate (inst/s) +host_op_rate 1769979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57024152249 # Simulator tick rate (ticks/s) +host_mem_usage 311592 # Number of bytes of host memory used +host_seconds 34.40 # Real time elapsed on the host +sim_insts 60892925 # Number of instructions simulated +sim_ops 60892925 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 833472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24887104 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 338304 # Number of bytes read from this memory -system.physmem.bytes_read::total 28741248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 833472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865152 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7743680 # Number of bytes written to this memory -system.physmem.bytes_written::total 7743680 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388861 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 495 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5286 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449082 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120995 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120995 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12691610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 172524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14657098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16156 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441199 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3949024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3949024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3949024 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12691610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 172524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18606122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449082 # Number of read requests accepted -system.physmem.writeReqs 120995 # Number of write requests accepted -system.physmem.readBursts 449082 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120995 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28737664 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue -system.physmem.bytesWritten 7742592 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28741248 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7743680 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 833088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24884096 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 31936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 337152 # Number of bytes read from this memory +system.physmem.bytes_read::total 28737152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 833088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7735232 # Number of bytes written to this memory +system.physmem.bytes_written::total 7735232 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388814 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5268 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449018 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120863 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120863 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12684231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 171857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14648258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424652 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16279 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3942899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3942899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3942899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12684231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 171857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18591157 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 449018 # Number of read requests accepted +system.physmem.writeReqs 120863 # Number of write requests accepted +system.physmem.readBursts 449018 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120863 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28729600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 7733952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28737152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7735232 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7094 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28167 # Per bank write bursts -system.physmem.perBankRdBursts::1 28459 # Per bank write bursts -system.physmem.perBankRdBursts::2 28057 # Per bank write bursts -system.physmem.perBankRdBursts::3 27664 # Per bank write bursts -system.physmem.perBankRdBursts::4 27762 # Per bank write bursts -system.physmem.perBankRdBursts::5 27793 # Per bank write bursts -system.physmem.perBankRdBursts::6 28259 # Per bank write bursts -system.physmem.perBankRdBursts::7 27872 # Per bank write bursts -system.physmem.perBankRdBursts::8 28083 # Per bank write bursts -system.physmem.perBankRdBursts::9 27730 # Per bank write bursts -system.physmem.perBankRdBursts::10 27672 # Per bank write bursts -system.physmem.perBankRdBursts::11 28135 # Per bank write bursts -system.physmem.perBankRdBursts::12 28179 # Per bank write bursts -system.physmem.perBankRdBursts::13 28505 # Per bank write bursts -system.physmem.perBankRdBursts::14 28654 # Per bank write bursts -system.physmem.perBankRdBursts::15 28035 # Per bank write bursts -system.physmem.perBankWrBursts::0 7928 # Per bank write bursts -system.physmem.perBankWrBursts::1 7868 # Per bank write bursts -system.physmem.perBankWrBursts::2 7543 # Per bank write bursts -system.physmem.perBankWrBursts::3 7157 # Per bank write bursts -system.physmem.perBankWrBursts::4 7275 # Per bank write bursts -system.physmem.perBankWrBursts::5 7314 # Per bank write bursts -system.physmem.perBankWrBursts::6 7747 # Per bank write bursts -system.physmem.perBankWrBursts::7 7251 # Per bank write bursts -system.physmem.perBankWrBursts::8 7322 # Per bank write bursts -system.physmem.perBankWrBursts::9 7110 # Per bank write bursts -system.physmem.perBankWrBursts::10 7099 # Per bank write bursts -system.physmem.perBankWrBursts::11 7523 # Per bank write bursts -system.physmem.perBankWrBursts::12 7681 # Per bank write bursts -system.physmem.perBankWrBursts::13 8141 # Per bank write bursts -system.physmem.perBankWrBursts::14 8335 # Per bank write bursts -system.physmem.perBankWrBursts::15 7684 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 6983 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28166 # Per bank write bursts +system.physmem.perBankRdBursts::1 28350 # Per bank write bursts +system.physmem.perBankRdBursts::2 28054 # Per bank write bursts +system.physmem.perBankRdBursts::3 27500 # Per bank write bursts +system.physmem.perBankRdBursts::4 27615 # Per bank write bursts +system.physmem.perBankRdBursts::5 27605 # Per bank write bursts +system.physmem.perBankRdBursts::6 28127 # Per bank write bursts +system.physmem.perBankRdBursts::7 27851 # Per bank write bursts +system.physmem.perBankRdBursts::8 28176 # Per bank write bursts +system.physmem.perBankRdBursts::9 27723 # Per bank write bursts +system.physmem.perBankRdBursts::10 27750 # Per bank write bursts +system.physmem.perBankRdBursts::11 28018 # Per bank write bursts +system.physmem.perBankRdBursts::12 28330 # Per bank write bursts +system.physmem.perBankRdBursts::13 28694 # Per bank write bursts +system.physmem.perBankRdBursts::14 28891 # Per bank write bursts +system.physmem.perBankRdBursts::15 28050 # Per bank write bursts +system.physmem.perBankWrBursts::0 7929 # Per bank write bursts +system.physmem.perBankWrBursts::1 7797 # Per bank write bursts +system.physmem.perBankWrBursts::2 7545 # Per bank write bursts +system.physmem.perBankWrBursts::3 7029 # Per bank write bursts +system.physmem.perBankWrBursts::4 7135 # Per bank write bursts +system.physmem.perBankWrBursts::5 7129 # Per bank write bursts +system.physmem.perBankWrBursts::6 7643 # Per bank write bursts +system.physmem.perBankWrBursts::7 7252 # Per bank write bursts +system.physmem.perBankWrBursts::8 7395 # Per bank write bursts +system.physmem.perBankWrBursts::9 7084 # Per bank write bursts +system.physmem.perBankWrBursts::10 7104 # Per bank write bursts +system.physmem.perBankWrBursts::11 7401 # Per bank write bursts +system.physmem.perBankWrBursts::12 7833 # Per bank write bursts +system.physmem.perBankWrBursts::13 8315 # Per bank write bursts +system.physmem.perBankWrBursts::14 8551 # Per bank write bursts +system.physmem.perBankWrBursts::15 7701 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1960902862500 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1961806557500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 449082 # Read request sizes (log2) +system.physmem.readPktSize::6 449018 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120995 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 409890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 987 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120863 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407987 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1052 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1527 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -143,456 +143,370 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 26 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49380 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 738.726934 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 222.746795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1735.319745 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 17723 35.89% 35.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 7354 14.89% 50.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4892 9.91% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2955 5.98% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1860 3.77% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1462 2.96% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1143 2.31% 75.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 851 1.72% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 746 1.51% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 676 1.37% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 661 1.34% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 443 0.90% 82.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 337 0.68% 83.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 276 0.56% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 300 0.61% 84.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 399 0.81% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 192 0.39% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 178 0.36% 85.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 196 0.40% 86.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 170 0.34% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 202 0.41% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 873 1.77% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 184 0.37% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 168 0.34% 89.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 96 0.19% 89.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 82 0.17% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 107 0.22% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 72 0.15% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 81 0.16% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 51 0.10% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 64 0.13% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 84 0.17% 90.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 51 0.10% 90.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 54 0.11% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 70 0.14% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 45 0.09% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 72 0.15% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 49 0.10% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 40 0.08% 91.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 72 0.15% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 42 0.09% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 45 0.09% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 69 0.14% 92.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 44 0.09% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 64 0.13% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 43 0.09% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 76 0.15% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 39 0.08% 92.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 46 0.09% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 67 0.14% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 46 0.09% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 66 0.13% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 46 0.09% 93.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 37 0.07% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 72 0.15% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 38 0.08% 93.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 42 0.09% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 69 0.14% 93.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 43 0.09% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 64 0.13% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 42 0.09% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 41 0.08% 94.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 74 0.15% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 37 0.07% 94.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 43 0.09% 94.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 66 0.13% 94.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 46 0.09% 94.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 64 0.13% 94.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 43 0.09% 94.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 37 0.07% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 404 0.82% 95.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 34 0.07% 95.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 44 0.09% 96.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 36 0.07% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 44 0.09% 96.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 34 0.07% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 44 0.09% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 33 0.07% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 41 0.08% 96.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 51 0.10% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 44 0.09% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 32 0.06% 96.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 40 0.08% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 37 0.07% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 43 0.09% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 35 0.07% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 40 0.08% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 33 0.07% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 47 0.10% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 34 0.07% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 43 0.09% 97.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 35 0.07% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 44 0.09% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 34 0.07% 97.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 44 0.09% 97.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 38 0.08% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 42 0.09% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 35 0.07% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 43 0.09% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 32 0.06% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 40 0.08% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 37 0.07% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 41 0.08% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 32 0.06% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 431 0.87% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 10 0.02% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 3 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 3 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 3 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 3 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 36 0.07% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 180 0.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49380 # Bytes accessed per row activation -system.physmem.totQLat 6346588750 # Total ticks spent queuing -system.physmem.totMemAccLat 14721193750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2245130000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6129475000 # Total ticks spent accessing banks -system.physmem.avgQLat 14134.12 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13650.60 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 48187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 641.951066 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 418.430190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 422.843508 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8213 17.04% 17.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7073 14.68% 31.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2891 6.00% 37.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1720 3.57% 41.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1328 2.76% 44.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 906 1.88% 45.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 669 1.39% 47.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 536 1.11% 48.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24851 51.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48187 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6896 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 65.095418 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2542.617511 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6893 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6896 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6896 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.523637 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.253710 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.981541 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4466 64.76% 64.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 342 4.96% 69.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 377 5.47% 75.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1323 19.19% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 32 0.46% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 16 0.23% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 12 0.17% 95.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 22 0.32% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 43 0.62% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 30 0.44% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 27 0.39% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 32 0.46% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 29 0.42% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 31 0.45% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 6 0.09% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 8 0.12% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 10 0.15% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 3 0.04% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 4 0.06% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 4 0.06% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 3 0.04% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 5 0.07% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 3 0.04% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 2 0.03% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 3 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 3 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 6 0.09% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 12 0.17% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 5 0.07% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 7 0.10% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 4 0.06% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 3 0.04% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 5 0.07% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 6 0.09% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6896 # Writes before turning the bus around for reads +system.physmem.totQLat 7845433250 # Total ticks spent queuing +system.physmem.totMemAccLat 16453873250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2244500000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6363940000 # Total ticks spent accessing banks +system.physmem.avgQLat 17477.02 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14176.74 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32784.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 36653.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.65 # Average write queue length when enqueuing -system.physmem.readRowHits 424775 # Number of row buffer hits during reads -system.physmem.writeRowHits 95849 # Number of row buffer hits during writes -system.physmem.readRowHitRate 94.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.22 # Row buffer hit rate for writes -system.physmem.avgGap 3439715.80 # Average gap between requests -system.physmem.pageHitRate 91.33 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.53 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 18666756 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292805 # Transaction distribution -system.membus.trans_dist::ReadResp 292805 # Transaction distribution -system.membus.trans_dist::WriteReq 14109 # Transaction distribution -system.membus.trans_dist::WriteResp 14109 # Transaction distribution -system.membus.trans_dist::Writeback 120995 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16488 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11559 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7097 # Transaction distribution -system.membus.trans_dist::ReadExReq 164894 # Transaction distribution -system.membus.trans_dist::ReadExResp 164048 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42616 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931055 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 973671 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124663 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124663 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1098334 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82290 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176960 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31259250 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307968 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5307968 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36567218 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36567218 # Total data (bytes) -system.membus.snoop_data_through_bus 36608 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 43251000 # Layer occupancy (ticks) +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.52 # Average write queue length when enqueuing +system.physmem.readRowHits 403422 # Number of row buffer hits during reads +system.physmem.writeRowHits 97436 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.62 # Row buffer hit rate for writes +system.physmem.avgGap 3442484.58 # Average gap between requests +system.physmem.pageHitRate 87.91 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.55 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18651494 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292756 # Transaction distribution +system.membus.trans_dist::ReadResp 292756 # Transaction distribution +system.membus.trans_dist::WriteReq 14067 # Transaction distribution +system.membus.trans_dist::WriteResp 14067 # Transaction distribution +system.membus.trans_dist::Writeback 120863 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16150 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11271 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6986 # Transaction distribution +system.membus.trans_dist::ReadExReq 164854 # Transaction distribution +system.membus.trans_dist::ReadExResp 164030 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42532 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 972562 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1097228 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 81954 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31164224 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31246178 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36554338 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36554338 # Total data (bytes) +system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 43154000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1579578000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1578633000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3830990646 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3834132000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376315500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376702000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 342160 # number of replacements -system.l2c.tags.tagsinuse 65219.945305 # Cycle average of tags in use -system.l2c.tags.total_refs 2443226 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407347 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.997899 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8615385750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55312.026017 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4807.093964 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4897.564051 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 159.017352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 44.243921 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.843995 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073350 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.074731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002426 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995177 # Average percentage of cache occupancy +system.l2c.tags.replacements 342098 # number of replacements +system.l2c.tags.tagsinuse 65220.106735 # Cycle average of tags in use +system.l2c.tags.total_refs 2445213 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407285 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.003690 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8658635750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55273.758884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4807.212496 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4935.163888 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 160.761256 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 43.210211 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.843411 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075305 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002453 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000659 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995180 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65187 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 761 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5186 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7242 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51881 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 784 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5254 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7171 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 51861 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994675 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25932224 # Number of tag accesses -system.l2c.tags.data_accesses 25932224 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 684719 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 664525 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 317383 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 107430 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774057 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 791641 # number of Writeback hits -system.l2c.Writeback_hits::total 791641 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 180 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 539 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 719 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 129054 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 42974 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172028 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 684719 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 793579 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 317383 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 150404 # number of demand (read+write) hits -system.l2c.demand_hits::total 1946085 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 684719 # number of overall hits -system.l2c.overall_hits::cpu0.data 793579 # number of overall hits -system.l2c.overall_hits::cpu1.inst 317383 # number of overall hits -system.l2c.overall_hits::cpu1.data 150404 # number of overall hits -system.l2c.overall_hits::total 1946085 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13026 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271672 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 503 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 242 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285443 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2949 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1793 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4742 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 919 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 927 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1846 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 117950 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5055 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123005 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13026 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 389622 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 503 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 5297 # number of demand (read+write) misses -system.l2c.demand_misses::total 408448 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13026 # number of overall misses -system.l2c.overall_misses::cpu0.data 389622 # number of overall misses -system.l2c.overall_misses::cpu1.inst 503 # number of overall misses -system.l2c.overall_misses::cpu1.data 5297 # number of overall misses -system.l2c.overall_misses::total 408448 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 997409492 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17552881248 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 35450000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 19470500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18605211240 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1291954 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 10252557 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 11544511 # number of UpgradeReq miss cycles +system.l2c.tags.tag_accesses 25954090 # Number of tag accesses +system.l2c.tags.data_accesses 25954090 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 690864 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 668298 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 311515 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 104210 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774887 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 792911 # number of Writeback hits +system.l2c.Writeback_hits::total 792911 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 529 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 713 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 40 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 64 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 130516 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 42247 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172763 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 690864 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 798814 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 311515 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 146457 # number of demand (read+write) hits +system.l2c.demand_hits::total 1947650 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 690864 # number of overall hits +system.l2c.overall_hits::cpu0.data 798814 # number of overall hits +system.l2c.overall_hits::cpu1.inst 311515 # number of overall hits +system.l2c.overall_hits::cpu1.data 146457 # number of overall hits +system.l2c.overall_hits::total 1947650 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13020 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 271630 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 507 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 237 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285394 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2952 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1737 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4689 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 888 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 909 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1797 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 117936 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5042 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122978 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13020 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 389566 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 507 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 5279 # number of demand (read+write) misses +system.l2c.demand_misses::total 408372 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13020 # number of overall misses +system.l2c.overall_misses::cpu0.data 389566 # number of overall misses +system.l2c.overall_misses::cpu1.inst 507 # number of overall misses +system.l2c.overall_misses::cpu1.data 5279 # number of overall misses +system.l2c.overall_misses::total 408372 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 958908741 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 17698605243 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 37880750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 17386000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 18712780734 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1103962 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 9942571 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 11046533 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 835964 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 163493 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 999457 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8264985252 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 387201489 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8652186741 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 997409492 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 25817866500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 35450000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 406671989 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 27257397981 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 997409492 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 25817866500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 35450000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 406671989 # number of overall miss cycles -system.l2c.overall_miss_latency::total 27257397981 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 697745 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 936197 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 317886 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 107672 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2059500 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 791641 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 791641 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3129 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2332 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5461 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 957 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 948 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1905 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 247004 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 48029 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295033 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 697745 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1183201 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 317886 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 155701 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2354533 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 697745 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1183201 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 317886 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 155701 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2354533 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018669 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.290187 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.001582 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002248 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138598 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942474 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.768868 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.868339 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.960293 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.977848 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.969029 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.477523 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.105249 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.416919 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018669 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.329295 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.001582 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.034020 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173473 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018669 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.329295 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.001582 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.034020 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173473 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76570.665745 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 64610.564386 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70477.137177 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 80456.611570 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 65180.127871 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 438.099017 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5718.102064 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2434.523619 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 909.645267 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 176.367853 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 541.417660 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70071.939398 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76597.722849 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 70340.122280 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 76570.665745 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 66263.882686 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 70477.137177 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 76774.020955 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 66734.071365 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 76570.665745 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 66263.882686 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 70477.137177 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 76774.020955 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 66734.071365 # average overall miss latency +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 161993 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 997957 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8071982510 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 364247989 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 8436230499 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 958908741 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 25770587753 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 37880750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 381633989 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 27149011233 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 958908741 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 25770587753 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 37880750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 381633989 # number of overall miss cycles +system.l2c.overall_miss_latency::total 27149011233 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 703884 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 939928 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 312022 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 104447 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2060281 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 792911 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 792911 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3136 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2266 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5402 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 928 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 933 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1861 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 248452 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 47289 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295741 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 703884 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1188380 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 312022 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 151736 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2356022 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 703884 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1188380 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 312022 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 151736 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2356022 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018497 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.288990 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.001625 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.002269 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.138522 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941327 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.766549 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.868012 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.956897 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974277 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.965610 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.474683 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.106621 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.415830 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018497 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.327813 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.001625 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.034791 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173331 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018497 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.327813 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.001625 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.034791 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173331 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73648.904839 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 65157.034359 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74715.483235 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 73358.649789 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 65568.234560 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 373.970867 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5723.990213 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2355.839838 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 941.400901 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 178.210121 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 555.346132 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68443.753476 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72242.758628 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 68599.509660 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 73648.904839 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 66152.045489 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 74715.483235 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 72292.856412 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 66481.079097 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 73648.904839 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 66152.045489 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 74715.483235 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 72292.856412 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 66481.079097 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,8 +515,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79475 # number of writebacks -system.l2c.writebacks::total 79475 # number of writebacks +system.l2c.writebacks::writebacks 79343 # number of writebacks +system.l2c.writebacks::total 79343 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits @@ -612,111 +526,111 @@ system.l2c.demand_mshr_hits::total 11 # nu system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13023 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 271672 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 495 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 242 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285432 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2949 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1793 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4742 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 919 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 927 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1846 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 117950 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 5055 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 123005 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13023 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 389622 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 495 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 5297 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 408437 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13023 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 389622 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 495 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 5297 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 408437 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 831386758 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14156096752 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 28603000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 16450000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15032536510 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29642946 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17939793 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 47582739 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9190919 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9270927 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 18461846 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6783022748 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 323366011 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7106388759 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 831386758 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 20939119500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 28603000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 339816011 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22138925269 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 831386758 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 20939119500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 28603000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 339816011 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22138925269 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373164500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17619000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1390783500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2154378500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 679235000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2833613500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527543000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 696854000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4224397000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018664 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290187 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001557 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002248 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.138593 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942474 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.768868 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.868339 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.960293 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.977848 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969029 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477523 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.105249 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.416919 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018664 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.329295 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001557 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.034020 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173468 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018664 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.329295 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001557 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.034020 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173468 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63839.880058 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52107.308637 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57783.838384 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67975.206612 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 52665.911706 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10051.863683 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10005.461796 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.318642 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 13017 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 271630 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 499 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 237 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285383 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2952 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1737 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4689 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 888 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 909 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1797 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 117936 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5042 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122978 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13017 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 389566 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 499 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 5279 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 408361 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13017 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 389566 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 499 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 5279 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 408361 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 793128009 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14302134757 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 30990750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 14431500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15140685016 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29678448 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17371737 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 47050185 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8880888 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9090909 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 17971797 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6590771990 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 300610511 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6891382501 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 793128009 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 20892906747 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 30990750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 315042011 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22032067517 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 793128009 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 20892906747 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 30990750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 315042011 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22032067517 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373162000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17619500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1390781500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2149958500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674822000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2824780500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3523120500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692441500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4215562000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018493 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.288990 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001599 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002269 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138517 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941327 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.766549 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.868012 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.956897 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974277 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.965610 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.474683 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.106621 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.415830 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018493 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.327813 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001599 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.034791 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173326 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018493 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.327813 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001599 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.034791 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173326 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52653.001351 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 60892.405063 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53053.913569 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.674797 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.161868 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57507.611259 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63969.537290 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 57773.169863 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63839.880058 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53742.138534 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57783.838384 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64152.541250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54204.014986 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63839.880058 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53742.138534 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57783.838384 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64152.541250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54204.014986 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55884.310050 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59621.283419 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56037.522980 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53631.237703 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59678.350256 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 53952.428163 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53631.237703 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59678.350256 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 53952.428163 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -728,14 +642,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.570482 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.569649 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1754531382000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.570482 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035655 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035655 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1755503918000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.569649 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035603 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035603 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -749,14 +663,14 @@ system.iocache.demand_misses::tsunami.ide 41726 # n system.iocache.demand_misses::total 41726 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21249133 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21249133 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12966402814 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12966402814 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12987651947 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12987651947 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12987651947 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12987651947 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21248883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21248883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 13129991411 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 13129991411 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13151240294 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13151240294 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13151240294 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13151240294 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -773,19 +687,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122121.454023 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122121.454023 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312052.435839 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 312052.435839 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 311260.411901 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 311260.411901 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 401197 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122120.017241 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122120.017241 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 315989.396684 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 315989.396684 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 315180.949384 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 315180.949384 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 388544 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28980 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28481 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.843927 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.642218 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -799,14 +713,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41726 system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12200133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12200133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10804136814 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10804136814 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10816336947 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10816336947 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10816336947 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10816336947 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12199883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10966952411 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10966952411 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10979152294 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10979152294 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10979152294 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10979152294 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -815,14 +729,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70115.706897 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70115.706897 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260014.844388 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 260014.844388 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70114.270115 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70114.270115 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 263933.202036 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 263933.202036 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -840,22 +754,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7532654 # DTB read hits -system.cpu0.dtb.read_misses 7812 # DTB read misses +system.cpu0.dtb.read_hits 7562587 # DTB read hits +system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 524694 # DTB read accesses -system.cpu0.dtb.write_hits 5120278 # DTB write hits -system.cpu0.dtb.write_misses 919 # DTB write misses -system.cpu0.dtb.write_acv 139 # DTB write access violations -system.cpu0.dtb.write_accesses 202960 # DTB write accesses -system.cpu0.dtb.data_hits 12652932 # DTB hits -system.cpu0.dtb.data_misses 8731 # DTB misses -system.cpu0.dtb.data_acv 349 # DTB access violations -system.cpu0.dtb.data_accesses 727654 # DTB accesses -system.cpu0.itb.fetch_hits 3655515 # ITB hits -system.cpu0.itb.fetch_misses 4023 # ITB misses +system.cpu0.dtb.read_accesses 524069 # DTB read accesses +system.cpu0.dtb.write_hits 5147352 # DTB write hits +system.cpu0.dtb.write_misses 910 # DTB write misses +system.cpu0.dtb.write_acv 133 # DTB write access violations +system.cpu0.dtb.write_accesses 202595 # DTB write accesses +system.cpu0.dtb.data_hits 12709939 # DTB hits +system.cpu0.dtb.data_misses 8675 # DTB misses +system.cpu0.dtb.data_acv 343 # DTB access violations +system.cpu0.dtb.data_accesses 726664 # DTB accesses +system.cpu0.itb.fetch_hits 3660806 # ITB hits +system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3659538 # ITB accesses +system.cpu0.itb.fetch_accesses 3664790 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -868,56 +782,56 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3921819749 # number of cpu cycles simulated +system.cpu0.numCycles 3923627139 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47983654 # Number of instructions committed -system.cpu0.committedOps 47983654 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44515044 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 211401 # Number of float alu accesses -system.cpu0.num_func_calls 1203620 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5635723 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44515044 # number of integer instructions -system.cpu0.num_fp_insts 211401 # number of float instructions -system.cpu0.num_int_register_reads 61226145 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33154260 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 103282 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 105080 # number of times the floating registers were written -system.cpu0.num_mem_refs 12694028 # number of memory refs -system.cpu0.num_load_insts 7560495 # Number of load instructions -system.cpu0.num_store_insts 5133533 # Number of store instructions -system.cpu0.num_idle_cycles 3698209766.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 223609982.001886 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057017 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942983 # Percentage of idle cycles -system.cpu0.Branches 7227606 # Number of branches fetched +system.cpu0.committedInsts 48127942 # Number of instructions committed +system.cpu0.committedOps 48127942 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44644072 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 213646 # Number of float alu accesses +system.cpu0.num_func_calls 1209779 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5646914 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44644072 # number of integer instructions +system.cpu0.num_fp_insts 213646 # number of float instructions +system.cpu0.num_int_register_reads 61387929 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33243119 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 104403 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 106204 # number of times the floating registers were written +system.cpu0.num_mem_refs 12751056 # number of memory refs +system.cpu0.num_load_insts 7590434 # Number of load instructions +system.cpu0.num_store_insts 5160622 # Number of store instructions +system.cpu0.num_idle_cycles 3699531471.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 224095667.001886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057114 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942886 # Percentage of idle cycles +system.cpu0.Branches 7246727 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165343 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56789 40.24% 40.24% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.33% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.40% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 435 0.31% 42.04% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 81806 57.96% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141134 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56279 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 166332 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 57240 40.25% 40.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.39% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82451 57.97% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 142220 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56707 49.09% 49.09% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 435 0.38% 51.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55844 48.70% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114662 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1901501471500 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 95150500 0.00% 96.98% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 767153500 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 322241000 0.02% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58223100500 2.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1960909117000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.991019 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1974 1.71% 50.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1902164041000 96.96% 96.96% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95225000 0.00% 96.96% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 767277500 0.04% 97.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 314374500 0.02% 97.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58471894000 2.98% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961812812000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682639 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812434 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682624 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812256 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -949,37 +863,37 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 517 0.35% 0.35% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.35% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.35% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.35% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3090 2.07% 2.42% # number of callpals executed -system.cpu0.kern.callpal::tbi 52 0.03% 2.45% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134176 89.74% 92.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6700 4.48% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal::rti 4418 2.95% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 396 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3107 2.06% 2.40% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed +system.cpu0.kern.callpal::swpipl 135267 89.81% 92.25% # number of callpals executed +system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149515 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7023 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1378 # number of protection mode switches +system.cpu0.kern.callpal::total 150615 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7022 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1377 -system.cpu0.kern.mode_good::user 1378 +system.cpu0.kern.mode_good::kernel 1371 +system.cpu0.kern.mode_good::user 1372 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.196070 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195244 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.327937 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1957102433500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3806679000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.326781 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958041026500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3771781000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3091 # number of times the context was actually changed +system.cpu0.kern.swap_context 3108 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1011,47 +925,47 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 103937669 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2101927 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2101912 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14109 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14109 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 791641 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16698 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11618 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28316 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 338479 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296929 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1395511 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121357 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 635773 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 463473 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5616114 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44655680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119473096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20344704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16974250 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 201447730 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 201437426 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2374976 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4790041400 # Layer occupancy (ticks) +system.toL2Bus.throughput 103965077 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2102306 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2102291 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 792911 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16363 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11335 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27698 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 339143 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297593 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407788 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134857 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624045 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452421 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5619111 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45048576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120057312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19969408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16548674 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 201623970 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 201613666 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2346432 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4795947858 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3142512505 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3170057255 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5519878863 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5536383084 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1430590492 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1404201241 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 794307231 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 776393157 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1399302 # Throughput (bytes/s) +system.iobus.throughput 1398487 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7373 # Transaction distribution system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55661 # Transaction distribution -system.iobus.trans_dist::WriteResp 55661 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14006 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 55619 # Transaction distribution +system.iobus.trans_dist::WriteResp 55619 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1063,11 +977,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42616 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126068 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56024 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1079,12 +993,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 82290 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2743906 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2743906 # Total data (bytes) -system.iobus.reqLayer0.occupancy 13361000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2743570 # Total data (bytes) +system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1106,67 +1020,67 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377744447 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380082294 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28507000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42681500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43185000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 697136 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.398756 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47294969 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 697648 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.792023 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 40091069250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.398756 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992966 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992966 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 703274 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.380970 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47433057 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 703786 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.396989 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40278267250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.380970 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992932 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992932 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48690501 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48690501 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47294969 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47294969 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47294969 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47294969 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47294969 # number of overall hits -system.cpu0.icache.overall_hits::total 47294969 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 697766 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 697766 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 697766 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 697766 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 697766 # number of overall misses -system.cpu0.icache.overall_misses::total 697766 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9984385005 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9984385005 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9984385005 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9984385005 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9984385005 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9984385005 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47992735 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47992735 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47992735 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47992735 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47992735 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47992735 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014539 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014539 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014539 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014539 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014539 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014539 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14309.073536 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.073536 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14309.073536 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14309.073536 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48840865 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48840865 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47433057 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47433057 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47433057 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47433057 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47433057 # number of overall hits +system.cpu0.icache.overall_hits::total 47433057 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 703904 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 703904 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 703904 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 703904 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 703904 # number of overall misses +system.cpu0.icache.overall_misses::total 703904 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10025783755 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10025783755 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10025783755 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10025783755 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10025783755 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10025783755 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 48136961 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 48136961 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 48136961 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 48136961 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 48136961 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 48136961 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014623 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014623 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014623 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014623 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014623 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014623 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14243.112349 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14243.112349 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14243.112349 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14243.112349 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14243.112349 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14243.112349 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1175,119 +1089,119 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697766 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 697766 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 697766 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 697766 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 697766 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 697766 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8583721995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8583721995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8583721995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8583721995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8583721995 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8583721995 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014539 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014539 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014539 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12301.720054 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 703904 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 703904 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 703904 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 703904 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 703904 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 703904 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8612997245 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8612997245 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8612997245 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8612997245 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8612997245 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8612997245 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014623 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014623 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014623 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12236.039638 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1186229 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.271614 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11460994 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1186741 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.657536 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 107902250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.271614 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986859 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986859 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 1191290 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.228160 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11513399 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1191802 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.660496 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 108508250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.228160 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986774 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986774 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51851796 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51851796 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6451735 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6451735 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4706856 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4706856 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140512 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140512 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148003 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148003 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11158591 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11158591 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11158591 # number of overall hits -system.cpu0.dcache.overall_hits::total 11158591 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 939483 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 939483 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 256736 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 256736 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13633 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13633 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5600 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5600 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1196219 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1196219 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1196219 # number of overall misses -system.cpu0.dcache.overall_misses::total 1196219 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27076055500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27076055500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10459807694 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10459807694 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 148332750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 148332750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43345419 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 43345419 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 37535863194 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 37535863194 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 37535863194 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 37535863194 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7391218 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7391218 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4963592 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4963592 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154145 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154145 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153603 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153603 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12354810 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12354810 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12354810 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12354810 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127108 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127108 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051724 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051724 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088443 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088443 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036458 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036458 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096822 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.096822 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096822 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.096822 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28820.165453 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28820.165453 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40741.492015 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40741.492015 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10880.418837 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10880.418837 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7740.253393 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7740.253393 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31378.755223 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31378.755223 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31378.755223 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31378.755223 # average overall miss latency +system.cpu0.dcache.tags.tag_accesses 52084916 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 52084916 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6477391 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6477391 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4731575 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4731575 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 141550 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 141550 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149263 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149263 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11208966 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11208966 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11208966 # number of overall hits +system.cpu0.dcache.overall_hits::total 11208966 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 942691 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 942691 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 258024 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 258024 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13717 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13717 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5452 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5452 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1200715 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1200715 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1200715 # number of overall misses +system.cpu0.dcache.overall_misses::total 1200715 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27259981257 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27259981257 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10282729939 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10282729939 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150891500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150891500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 41989388 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 41989388 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37542711196 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37542711196 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37542711196 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37542711196 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7420082 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7420082 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4989599 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4989599 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 155267 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 155267 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 154715 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 154715 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12409681 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12409681 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12409681 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12409681 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127046 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127046 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051712 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051712 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088345 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088345 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035239 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035239 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096756 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.096756 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096756 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096756 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28917.196894 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28917.196894 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39851.835252 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39851.835252 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11000.328060 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11000.328060 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7701.648569 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7701.648569 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31266.962765 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31266.962765 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1296,66 +1210,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682519 # number of writebacks -system.cpu0.dcache.writebacks::total 682519 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939483 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 939483 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256736 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 256736 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13633 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13633 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5600 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5600 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196219 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1196219 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196219 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1196219 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25065202500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25065202500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9891526306 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9891526306 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121052250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121052250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32145581 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32145581 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34956728806 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 34956728806 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34956728806 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 34956728806 # number of overall MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 686471 # number of writebacks +system.cpu0.dcache.writebacks::total 686471 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942691 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 942691 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 258024 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 258024 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13717 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13717 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5452 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5452 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1200715 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1200715 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1200715 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1200715 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25249299743 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25249299743 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9714288061 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9714288061 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 123443500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 123443500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31083612 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31083612 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34963587804 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34963587804 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34963587804 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34963587804 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465602000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465602000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284723500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284723500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750325500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750325500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127108 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127108 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051724 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051724 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088443 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088443 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036458 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036458 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096822 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096822 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26679.782923 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26679.782923 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38528.006614 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38528.006614 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8879.355241 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8879.355241 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5740.282321 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5740.282321 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2280051500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2280051500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3745653500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3745653500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051712 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051712 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088345 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088345 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035239 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035239 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096756 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096756 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096756 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096756 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26784.280048 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26784.280048 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37648.777094 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37648.777094 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8999.307429 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8999.307429 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5701.322817 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5701.322817 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29118.973115 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29118.973115 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29118.973115 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29118.973115 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1367,22 +1277,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2383442 # DTB read hits +system.cpu1.dtb.read_hits 2348422 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1706844 # DTB write hits +system.cpu1.dtb.write_hits 1677006 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4090286 # DTB hits +system.cpu1.dtb.data_hits 4025428 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1814139 # ITB hits +system.cpu1.itb.fetch_hits 1801062 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1815203 # ITB accesses +system.cpu1.itb.fetch_accesses 1802126 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1395,52 +1305,52 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3919927793 # number of cpu cycles simulated +system.cpu1.numCycles 3921881188 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12950293 # Number of instructions committed -system.cpu1.committedOps 12950293 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11929999 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 174217 # Number of float alu accesses -system.cpu1.num_func_calls 410658 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1281658 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11929999 # number of integer instructions -system.cpu1.num_fp_insts 174217 # number of float instructions -system.cpu1.num_int_register_reads 16394755 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8774296 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90513 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92474 # number of times the floating registers were written -system.cpu1.num_mem_refs 4113222 # number of memory refs -system.cpu1.num_load_insts 2397194 # Number of load instructions -system.cpu1.num_store_insts 1716028 # Number of store instructions -system.cpu1.num_idle_cycles 3870487590.349789 # Number of idle cycles -system.cpu1.num_busy_cycles 49440202.650211 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles -system.cpu1.Branches 1846576 # Number of branches fetched +system.cpu1.committedInsts 12764983 # Number of instructions committed +system.cpu1.committedOps 12764983 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11763372 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses +system.cpu1.num_func_calls 404056 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1265589 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11763372 # number of integer instructions +system.cpu1.num_fp_insts 170364 # number of float instructions +system.cpu1.num_int_register_reads 16177579 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8656447 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written +system.cpu1.num_mem_refs 4047975 # number of memory refs +system.cpu1.num_load_insts 2361944 # Number of load instructions +system.cpu1.num_store_insts 1686031 # Number of store instructions +system.cpu1.num_idle_cycles 3873256564.808130 # Number of idle cycles +system.cpu1.num_busy_cycles 48624623.191870 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012398 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987602 # Percentage of idle cycles +system.cpu1.Branches 1821589 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78268 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26619 38.27% 38.27% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.83% 41.10% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 517 0.74% 41.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40454 58.16% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69559 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25752 48.16% 48.16% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.68% 51.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 517 0.97% 52.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25236 47.19% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53474 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1908686801000 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700508000 0.04% 97.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 362068000 0.02% 97.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50214489500 2.56% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1959963866500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967429 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2741 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77081 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26132 38.19% 38.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 39821 58.19% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 68428 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25288 48.13% 48.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 24782 47.16% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 52545 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909614205500 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700881500 0.04% 97.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 353850000 0.02% 97.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50271627000 2.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1960940564000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967702 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.623820 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.768757 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.622335 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.767887 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1456,87 +1366,87 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 435 0.61% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2001 2.79% 3.40% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed -system.cpu1.kern.callpal::swpipl 63355 88.19% 91.60% # number of callpals executed -system.cpu1.kern.callpal::rdps 2145 2.99% 94.59% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.59% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.59% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::rti 3718 5.18% 99.77% # number of callpals executed +system.cpu1.kern.callpal::wripir 424 0.60% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62267 88.12% 91.51% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 3.04% 94.54% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.54% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.55% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.55% # number of callpals executed +system.cpu1.kern.callpal::rti 3685 5.22% 99.77% # number of callpals executed system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71838 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1956 # number of protection mode switches +system.cpu1.kern.callpal::total 70661 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1917 # number of protection mode switches system.cpu1.kern.mode_switch::user 368 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2906 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 809 +system.cpu1.kern.mode_switch::idle 2889 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 798 system.cpu1.kern.mode_good::user 368 -system.cpu1.kern.mode_good::idle 441 -system.cpu1.kern.mode_switch_good::kernel 0.413599 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 430 +system.cpu1.kern.mode_switch_good::kernel 0.416275 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.151755 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309369 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17986814000 0.92% 0.92% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1484472500 0.08% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1939632240000 99.01% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2002 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 317336 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.450379 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12635285 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 317847 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.752727 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1958987590000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.450379 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871973 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.871973 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.148840 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.308465 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17543884000 0.90% 0.90% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1484004500 0.08% 0.97% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1941017048000 99.03% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1956 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 311472 # number of replacements +system.cpu1.icache.tags.tagsinuse 449.263709 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12455839 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 311983 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.924736 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1960006992500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 449.263709 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.877468 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.877468 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 437 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13271059 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13271059 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12635285 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12635285 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12635285 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12635285 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12635285 # number of overall hits -system.cpu1.icache.overall_hits::total 12635285 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 317887 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 317887 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 317887 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 317887 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 317887 # number of overall misses -system.cpu1.icache.overall_misses::total 317887 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4180819492 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4180819492 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4180819492 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4180819492 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4180819492 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4180819492 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953172 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12953172 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12953172 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12953172 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12953172 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12953172 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024541 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024541 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024541 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024541 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024541 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024541 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13151.904582 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13151.904582 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13151.904582 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13151.904582 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13079885 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13079885 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12455839 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12455839 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12455839 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12455839 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12455839 # number of overall hits +system.cpu1.icache.overall_hits::total 12455839 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 312023 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 312023 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 312023 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 312023 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 312023 # number of overall misses +system.cpu1.icache.overall_misses::total 312023 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4106650741 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4106650741 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4106650741 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4106650741 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4106650741 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4106650741 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12767862 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12767862 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12767862 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12767862 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12767862 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12767862 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024438 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024438 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024438 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024438 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024438 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024438 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13161.371889 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13161.371889 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13161.371889 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13161.371889 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1545,118 +1455,118 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317887 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 317887 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 317887 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 317887 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 317887 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 317887 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3544847508 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3544847508 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3544847508 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3544847508 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3544847508 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3544847508 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024541 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024541 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024541 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11151.281770 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312023 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 312023 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 312023 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 312023 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 312023 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 312023 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3482409259 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3482409259 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3482409259 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3482409259 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3482409259 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3482409259 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024438 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024438 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024438 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11160.745391 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11160.745391 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11160.745391 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 158764 # number of replacements -system.cpu1.dcache.tags.tagsinuse 485.752776 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3916687 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 159090 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.619316 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 67802253000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.752776 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948736 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.948736 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 326 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.636719 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16587420 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16587420 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2220669 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2220669 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1595283 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1595283 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48031 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48031 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50613 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50613 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3815952 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3815952 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3815952 # number of overall hits -system.cpu1.dcache.overall_hits::total 3815952 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 116704 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 116704 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 56889 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 56889 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9081 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9081 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6019 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6019 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 173593 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 173593 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 173593 # number of overall misses -system.cpu1.dcache.overall_misses::total 173593 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1411486000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1411486000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1044020804 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1044020804 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82357000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 82357000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44184927 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 44184927 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2455506804 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2455506804 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2455506804 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2455506804 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2337373 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2337373 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1652172 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1652172 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57112 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 57112 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56632 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56632 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3989545 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3989545 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3989545 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3989545 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049930 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049930 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034433 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034433 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159003 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159003 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106283 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106283 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043512 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043512 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043512 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043512 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12094.581163 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12094.581163 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18351.892352 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18351.892352 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9069.155379 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9069.155379 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7340.908290 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7340.908290 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14145.194818 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14145.194818 # average overall miss latency +system.cpu1.dcache.tags.replacements 155135 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.308895 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3855441 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 155464 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.799574 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1048852146500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.308895 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949822 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949822 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 16322717 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16322717 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2189668 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2189668 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1567568 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1567568 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 46969 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 46969 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 49480 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 49480 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3757236 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3757236 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3757236 # number of overall hits +system.cpu1.dcache.overall_hits::total 3757236 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 113735 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 113735 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 55930 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 55930 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8863 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8863 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5883 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5883 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 169665 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 169665 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 169665 # number of overall misses +system.cpu1.dcache.overall_misses::total 169665 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1371834000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1371834000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1009197248 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1009197248 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80472000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 80472000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43306909 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 43306909 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2381031248 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2381031248 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2381031248 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2381031248 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2303403 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2303403 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1623498 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1623498 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 55832 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 55832 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 55363 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 55363 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3926901 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3926901 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3926901 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3926901 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049377 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049377 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034450 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034450 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158744 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158744 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106262 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106262 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043206 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043206 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043206 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043206 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.669671 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.669671 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18043.934347 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18043.934347 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9079.544172 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9079.544172 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.364780 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.364780 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14033.720850 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14033.720850 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14033.720850 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14033.720850 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1665,62 +1575,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 109122 # number of writebacks -system.cpu1.dcache.writebacks::total 109122 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116704 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 116704 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 56889 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 56889 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9081 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9081 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6019 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6019 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 173593 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 173593 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 173593 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 173593 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1178000000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1178000000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 927938196 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 927938196 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64195000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64195000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32145073 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32145073 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2105938196 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2105938196 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2105938196 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2105938196 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718207000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718207000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 736983000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 736983000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049930 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049930 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034433 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034433 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159003 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159003 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106283 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106283 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043512 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043512 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10093.912805 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10093.912805 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16311.381743 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16311.381743 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7069.155379 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7069.155379 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5340.600266 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5340.600266 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 106440 # number of writebacks +system.cpu1.dcache.writebacks::total 106440 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113735 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 113735 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55930 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 55930 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8863 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8863 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 169665 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 169665 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 169665 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 169665 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144290000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144290000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 895105752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 895105752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62746000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62746000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31539091 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31539091 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2039395752 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2039395752 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2039395752 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2039395752 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713537000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713537000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732313500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732313500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049377 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049377 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158744 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158744 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106262 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106262 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043206 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043206 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.019035 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.019035 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16004.036331 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16004.036331 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.544172 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.544172 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.055754 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.055754 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 1efa023f6..5b0dc7b99 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,127 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920428 # Number of seconds simulated -sim_ticks 1920428041000 # Number of ticks simulated -final_tick 1920428041000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920416 # Number of seconds simulated +sim_ticks 1920416181000 # Number of ticks simulated +final_tick 1920416181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1405906 # Simulator instruction rate (inst/s) -host_op_rate 1405905 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48056353161 # Simulator tick rate (ticks/s) -host_mem_usage 307800 # Number of bytes of host memory used -host_seconds 39.96 # Real time elapsed on the host -sim_insts 56182750 # Number of instructions simulated -sim_ops 56182750 # Number of ops (including micro ops) simulated +host_inst_rate 1752736 # Simulator instruction rate (inst/s) +host_op_rate 1752735 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59896862792 # Simulator tick rate (ticks/s) +host_mem_usage 308520 # Number of bytes of host memory used +host_seconds 32.06 # Real time elapsed on the host +sim_insts 56196255 # Number of instructions simulated +sim_ops 56196255 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24846912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28349952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7389824 # Number of bytes written to this memory -system.physmem.bytes_written::total 7389824 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388233 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28363328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7405888 # Number of bytes written to this memory +system.physmem.bytes_written::total 7405888 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442968 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115466 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115466 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12938216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1381125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14762309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3848009 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3848009 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3848009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12938216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1381125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18610318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442968 # Number of read requests accepted -system.physmem.writeReqs 115466 # Number of write requests accepted -system.physmem.readBursts 442968 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115466 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28346688 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3264 # Total number of bytes read from write queue -system.physmem.bytesWritten 7389440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28349952 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7389824 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 51 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 443177 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115717 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115717 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 443004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12945227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1381134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14769365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 443004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3856397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3856397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3856397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 443004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12945227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1381134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18625763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443177 # Number of read requests accepted +system.physmem.writeReqs 115717 # Number of write requests accepted +system.physmem.readBursts 443177 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115717 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28355584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue +system.physmem.bytesWritten 7404416 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28363328 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7405888 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27966 # Per bank write bursts -system.physmem.perBankRdBursts::1 28089 # Per bank write bursts -system.physmem.perBankRdBursts::2 28297 # Per bank write bursts -system.physmem.perBankRdBursts::3 28053 # Per bank write bursts -system.physmem.perBankRdBursts::4 27407 # Per bank write bursts -system.physmem.perBankRdBursts::5 27545 # Per bank write bursts -system.physmem.perBankRdBursts::6 26911 # Per bank write bursts -system.physmem.perBankRdBursts::7 26762 # Per bank write bursts -system.physmem.perBankRdBursts::8 27807 # Per bank write bursts -system.physmem.perBankRdBursts::9 27255 # Per bank write bursts -system.physmem.perBankRdBursts::10 27714 # Per bank write bursts -system.physmem.perBankRdBursts::11 27327 # Per bank write bursts -system.physmem.perBankRdBursts::12 27431 # Per bank write bursts -system.physmem.perBankRdBursts::13 28073 # Per bank write bursts -system.physmem.perBankRdBursts::14 28024 # Per bank write bursts -system.physmem.perBankRdBursts::15 28256 # Per bank write bursts -system.physmem.perBankWrBursts::0 7722 # Per bank write bursts -system.physmem.perBankWrBursts::1 7593 # Per bank write bursts -system.physmem.perBankWrBursts::2 7833 # Per bank write bursts -system.physmem.perBankWrBursts::3 7543 # Per bank write bursts -system.physmem.perBankWrBursts::4 7010 # Per bank write bursts -system.physmem.perBankWrBursts::5 6982 # Per bank write bursts -system.physmem.perBankWrBursts::6 6469 # Per bank write bursts -system.physmem.perBankWrBursts::7 6223 # Per bank write bursts -system.physmem.perBankWrBursts::8 7224 # Per bank write bursts -system.physmem.perBankWrBursts::9 6661 # Per bank write bursts -system.physmem.perBankWrBursts::10 7099 # Per bank write bursts -system.physmem.perBankWrBursts::11 6780 # Per bank write bursts -system.physmem.perBankWrBursts::12 7009 # Per bank write bursts -system.physmem.perBankWrBursts::13 7722 # Per bank write bursts -system.physmem.perBankWrBursts::14 7773 # Per bank write bursts -system.physmem.perBankWrBursts::15 7817 # Per bank write bursts +system.physmem.perBankRdBursts::0 27851 # Per bank write bursts +system.physmem.perBankRdBursts::1 28132 # Per bank write bursts +system.physmem.perBankRdBursts::2 28319 # Per bank write bursts +system.physmem.perBankRdBursts::3 28010 # Per bank write bursts +system.physmem.perBankRdBursts::4 27531 # Per bank write bursts +system.physmem.perBankRdBursts::5 27552 # Per bank write bursts +system.physmem.perBankRdBursts::6 26732 # Per bank write bursts +system.physmem.perBankRdBursts::7 26855 # Per bank write bursts +system.physmem.perBankRdBursts::8 27890 # Per bank write bursts +system.physmem.perBankRdBursts::9 27110 # Per bank write bursts +system.physmem.perBankRdBursts::10 27744 # Per bank write bursts +system.physmem.perBankRdBursts::11 27465 # Per bank write bursts +system.physmem.perBankRdBursts::12 27482 # Per bank write bursts +system.physmem.perBankRdBursts::13 28199 # Per bank write bursts +system.physmem.perBankRdBursts::14 28116 # Per bank write bursts +system.physmem.perBankRdBursts::15 28068 # Per bank write bursts +system.physmem.perBankWrBursts::0 7630 # Per bank write bursts +system.physmem.perBankWrBursts::1 7636 # Per bank write bursts +system.physmem.perBankWrBursts::2 7854 # Per bank write bursts +system.physmem.perBankWrBursts::3 7535 # Per bank write bursts +system.physmem.perBankWrBursts::4 7127 # Per bank write bursts +system.physmem.perBankWrBursts::5 6994 # Per bank write bursts +system.physmem.perBankWrBursts::6 6317 # Per bank write bursts +system.physmem.perBankWrBursts::7 6319 # Per bank write bursts +system.physmem.perBankWrBursts::8 7309 # Per bank write bursts +system.physmem.perBankWrBursts::9 6529 # Per bank write bursts +system.physmem.perBankWrBursts::10 7110 # Per bank write bursts +system.physmem.perBankWrBursts::11 6915 # Per bank write bursts +system.physmem.perBankWrBursts::12 7060 # Per bank write bursts +system.physmem.perBankWrBursts::13 7819 # Per bank write bursts +system.physmem.perBankWrBursts::14 7860 # Per bank write bursts +system.physmem.perBankWrBursts::15 7680 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 1920416169000 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1920404309000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 442968 # Read request sizes (log2) +system.physmem.readPktSize::6 443177 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115466 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 403787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115717 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3793 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1793 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -133,289 +133,205 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 46254 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 772.575777 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.901205 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1785.674907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 16351 35.35% 35.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6669 14.42% 49.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4598 9.94% 59.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2705 5.85% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1760 3.81% 69.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1480 3.20% 72.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1070 2.31% 74.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 848 1.83% 76.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 733 1.58% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 614 1.33% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 629 1.36% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 417 0.90% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 327 0.71% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 305 0.66% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 281 0.61% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 335 0.72% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 208 0.45% 85.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 173 0.37% 85.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 157 0.34% 85.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 138 0.30% 86.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 163 0.35% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 903 1.95% 88.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 167 0.36% 88.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 98 0.21% 88.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 103 0.22% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 86 0.19% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 86 0.19% 89.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 55 0.12% 89.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 76 0.16% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 70 0.15% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 69 0.15% 90.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 49 0.11% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 76 0.16% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 62 0.13% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 63 0.14% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 35 0.08% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 62 0.13% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 58 0.13% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 65 0.14% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 35 0.08% 91.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 74 0.16% 91.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 59 0.13% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 59 0.13% 91.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 26 0.06% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 59 0.13% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 60 0.13% 91.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 63 0.14% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 34 0.07% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 64 0.14% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 58 0.13% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 54 0.12% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 33 0.07% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 54 0.12% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 58 0.13% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 64 0.14% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 34 0.07% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 65 0.14% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 57 0.12% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 56 0.12% 93.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 28 0.06% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 54 0.12% 93.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 53 0.11% 93.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 65 0.14% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 67 0.14% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 53 0.11% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 55 0.12% 94.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 27 0.06% 94.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 54 0.12% 94.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 56 0.12% 94.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 66 0.14% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 372 0.80% 95.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 49 0.11% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 28 0.06% 95.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 48 0.10% 95.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 28 0.06% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 51 0.11% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 28 0.06% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 52 0.11% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 28 0.06% 96.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 51 0.11% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 40 0.09% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 53 0.11% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 25 0.05% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 51 0.11% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 26 0.06% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 51 0.11% 96.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 24 0.05% 96.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 50 0.11% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 28 0.06% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 50 0.11% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 26 0.06% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 50 0.11% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 27 0.06% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 51 0.11% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 28 0.06% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 50 0.11% 97.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 26 0.06% 97.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 49 0.11% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 26 0.06% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 52 0.11% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 25 0.05% 98.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 52 0.11% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 25 0.05% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 52 0.11% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 425 0.92% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 13 0.03% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 4 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 3 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 35 0.08% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 180 0.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 46254 # Bytes accessed per row activation -system.physmem.totQLat 6257775000 # Total ticks spent queuing -system.physmem.totMemAccLat 14505282500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2214585000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6032922500 # Total ticks spent accessing banks -system.physmem.avgQLat 14128.55 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13620.89 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 46117 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 658.429646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 435.074403 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 420.347464 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7559 16.39% 16.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6338 13.74% 30.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2663 5.77% 35.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1600 3.47% 39.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1319 2.86% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 861 1.87% 44.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 594 1.29% 45.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 461 1.00% 46.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24722 53.61% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 46117 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6598 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 67.149288 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2598.278449 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6595 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6598 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6598 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.534707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.278859 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.820387 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4179 63.34% 63.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 322 4.88% 68.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 428 6.49% 74.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1303 19.75% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 22 0.33% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 17 0.26% 95.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 11 0.17% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 27 0.41% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 43 0.65% 96.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 28 0.42% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 21 0.32% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 25 0.38% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 19 0.29% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 43 0.65% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.06% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 12 0.18% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 10 0.15% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.02% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 5 0.08% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 4 0.06% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 4 0.06% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 5 0.08% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 2 0.03% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 9 0.14% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 4 0.06% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 4 0.06% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 2 0.03% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 3 0.05% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 6 0.09% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 8 0.12% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 5 0.08% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 6 0.09% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 3 0.05% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 4 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6598 # Writes before turning the bus around for reads +system.physmem.totQLat 7790286250 # Total ticks spent queuing +system.physmem.totMemAccLat 16274878750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2215280000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6269312500 # Total ticks spent accessing banks +system.physmem.avgQLat 17583.07 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14150.16 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32749.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.76 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.76 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 36733.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.25 # Average write queue length when enqueuing -system.physmem.readRowHits 419360 # Number of row buffer hits during reads -system.physmem.writeRowHits 92763 # Number of row buffer hits during writes -system.physmem.readRowHitRate 94.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.34 # Row buffer hit rate for writes -system.physmem.avgGap 3438931.31 # Average gap between requests -system.physmem.pageHitRate 91.72 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 18651952 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292310 # Transaction distribution -system.membus.trans_dist::ReadResp 292310 # Transaction distribution +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.59 # Average write queue length when enqueuing +system.physmem.readRowHits 398457 # Number of row buffer hits during reads +system.physmem.writeRowHits 94179 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.39 # Row buffer hit rate for writes +system.physmem.avgGap 3436079.67 # Average gap between requests +system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.57 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18667397 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292363 # Transaction distribution +system.membus.trans_dist::ReadResp 292363 # Transaction distribution system.membus.trans_dist::WriteReq 9650 # Transaction distribution system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115466 # Transaction distribution +system.membus.trans_dist::Writeback 115717 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 158141 # Transaction distribution -system.membus.trans_dist::ReadExResp 158141 # Transaction distribution +system.membus.trans_dist::ReadExReq 158297 # Transaction distribution +system.membus.trans_dist::ReadExResp 158297 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877537 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911366 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1035377 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1036046 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30430656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475220 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30460096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30504660 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 35784340 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35784340 # Total data (bytes) +system.membus.tot_pkt_size::total 35813780 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35813780 # Total data (bytes) system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1489694250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1492987250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3746415596 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3752965347 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376299750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376688000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.352288 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.344147 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753529489000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.352288 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1754500427000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.344147 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084009 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084009 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -429,14 +345,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12989922573 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12989922573 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13011056956 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13011056956 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13011056956 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13011056956 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21134633 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21134633 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 13148459442 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 13148459442 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13169594075 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13169594075 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13169594075 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13169594075 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -453,19 +369,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312618.467775 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 312618.467775 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 311828.806615 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 311828.806615 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 403484 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122165.508671 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122165.508671 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316433.852570 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 316433.852570 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 315628.378071 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 315628.378071 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 393896 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 29141 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28296 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.845922 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.920554 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -479,14 +395,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10827670073 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10827670073 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10839807456 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10839807456 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10839807456 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10839807456 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137633 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12137633 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10985430442 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10985430442 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10997568075 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10997568075 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10997568075 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10997568075 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -495,14 +411,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260581.201218 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 260581.201218 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70159.728324 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70159.728324 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264377.898585 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 264377.898585 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -521,22 +437,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9064966 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9066711 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6356267 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.write_hits 6357503 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15421233 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15424214 # DTB hits +system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973920 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020784 # DTB accesses +system.cpu.itb.fetch_hits 4974520 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978917 # ITB accesses +system.cpu.itb.fetch_accesses 4979530 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -549,52 +465,52 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3840856082 # number of cpu cycles simulated +system.cpu.numCycles 3840832362 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56182750 # Number of instructions committed -system.cpu.committedOps 56182750 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52054772 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses -system.cpu.num_func_calls 1483342 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468084 # number of instructions that are conditional controls -system.cpu.num_int_insts 52054772 # number of integer instructions -system.cpu.num_fp_insts 324326 # number of float instructions -system.cpu.num_int_register_reads 71321847 # number of times the integer registers were read -system.cpu.num_int_register_writes 38521555 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written -system.cpu.num_mem_refs 15473812 # number of memory refs -system.cpu.num_load_insts 9101789 # Number of load instructions -system.cpu.num_store_insts 6372023 # Number of store instructions -system.cpu.num_idle_cycles 3588896828.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251959253.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065600 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934400 # Percentage of idle cycles -system.cpu.Branches 8421946 # Number of branches fetched +system.cpu.committedInsts 56196255 # Number of instructions committed +system.cpu.committedOps 56196255 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52067788 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1483738 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469789 # number of instructions that are conditional controls +system.cpu.num_int_insts 52067788 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71342399 # number of times the integer registers were read +system.cpu.num_int_register_writes 38531411 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15476821 # number of memory refs +system.cpu.num_load_insts 9103557 # Number of load instructions +system.cpu.num_store_insts 6373264 # Number of store instructions +system.cpu.num_idle_cycles 3589010980.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251821381.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065564 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934436 # Percentage of idle cycles +system.cpu.Branches 8424076 # Number of branches fetched system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211963 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212001 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106216 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183174 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183184 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858257404500 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91623500 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737068500 0.04% 96.81% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61341210500 3.19% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920427307000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149127 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858066400000 96.75% 96.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91407000 0.00% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737349500 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61520290500 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920415447000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692250 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814084 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692248 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814083 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -630,10 +546,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175953 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175963 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -642,21 +558,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192898 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.callpal::total 192909 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1739 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323225 # fraction of useful protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323679 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391907 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46222890000 2.41% 2.41% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5212630500 0.27% 2.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1868991784500 97.32% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4176 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46067941500 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5182686000 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869164817500 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -688,7 +604,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1409150 # Throughput (bytes/s) +system.iobus.throughput 1409159 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51202 # Transaction distribution @@ -748,67 +664,67 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377727206 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380034075 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42674250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43162000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 928358 # number of replacements -system.cpu.icache.tags.tagsinuse 508.321671 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55265541 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928869 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.497670 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 39723654250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.321671 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992816 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992816 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928494 # number of replacements +system.cpu.icache.tags.tagsinuse 508.301721 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55278924 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929005 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.503365 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 39895254250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.301721 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992777 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57123599 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57123599 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55265541 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55265541 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55265541 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55265541 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55265541 # number of overall hits -system.cpu.icache.overall_hits::total 55265541 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929029 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929029 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929029 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929029 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929029 # number of overall misses -system.cpu.icache.overall_misses::total 929029 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12961853258 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12961853258 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12961853258 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12961853258 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12961853258 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12961853258 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56194570 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56194570 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56194570 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56194570 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56194570 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56194570 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13952.043755 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13952.043755 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13952.043755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13952.043755 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57137254 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57137254 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55278924 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55278924 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55278924 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55278924 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55278924 # number of overall hits +system.cpu.icache.overall_hits::total 55278924 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929165 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929165 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929165 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929165 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929165 # number of overall misses +system.cpu.icache.overall_misses::total 929165 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12919006759 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12919006759 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12919006759 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12919006759 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12919006759 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12919006759 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56208089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56208089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56208089 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56208089 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56208089 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56208089 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016531 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016531 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016531 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016531 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016531 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016531 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.888716 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13903.888716 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13903.888716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13903.888716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -817,135 +733,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929029 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929029 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929029 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929029 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929029 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929029 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11098555742 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11098555742 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11098555742 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11098555742 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11098555742 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11098555742 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11946.403979 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11946.403979 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929165 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929165 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929165 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929165 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929165 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929165 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11055577241 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11055577241 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11055577241 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11055577241 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11055577241 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11055577241 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016531 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016531 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016531 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.400436 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.400436 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.400436 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.400436 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.400436 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.400436 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336056 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65296.863719 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2447536 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401218 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.100265 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6747777750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55582.845445 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4758.900638 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4955.117636 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.848127 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072615 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.075609 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996351 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 336265 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65295.577509 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2447728 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401427 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.097567 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6793166750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 55588.679267 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4757.001179 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4949.897063 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.848216 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072586 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.075529 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996331 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1050 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4896 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3257 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55781 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4882 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3251 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55777 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 25947571 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 25947571 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 915717 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 814814 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1730531 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 835114 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 835114 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 25952661 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 25952661 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 915852 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 814775 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1730627 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 835359 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 835359 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187645 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187645 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 915717 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002459 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1918176 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 915717 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002459 # number of overall hits -system.cpu.l2cache.overall_hits::total 1918176 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 271915 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 285207 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187681 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187681 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 915852 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1002456 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918308 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 915852 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1002456 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918308 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 13293 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 271967 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 285260 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116708 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116708 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13292 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388623 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 401915 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13292 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388623 # number of overall misses -system.cpu.l2cache.overall_misses::total 401915 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1012336742 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17564329991 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18576666733 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_misses::cpu.data 116864 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116864 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13293 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388831 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 402124 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13293 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388831 # number of overall misses +system.cpu.l2cache.overall_misses::total 402124 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 967872241 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17714808491 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18682680732 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8190852374 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8190852374 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1012336742 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 25755182365 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26767519107 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1012336742 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 25755182365 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26767519107 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 929009 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1086729 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2015738 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 835114 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 835114 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8011039626 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8011039626 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 967872241 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 25725848117 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26693720358 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 967872241 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 25725848117 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26693720358 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 929145 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1086742 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2015887 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 835359 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 835359 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304353 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304353 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 929009 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1391082 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2320091 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 929009 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1391082 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2320091 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014308 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250214 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141490 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304545 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304545 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 929145 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1391287 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320432 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 929145 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1391287 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320432 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014307 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250259 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.141506 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383463 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383463 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014308 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279367 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173232 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014308 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279367 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173232 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76161.355853 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64594.928529 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 65133.978945 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383733 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383733 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014307 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279476 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173297 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014307 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279476 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173297 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72810.670353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65135.874908 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 65493.517254 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70182.441426 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70182.441426 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66599.950504 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66599.950504 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68550.106329 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68550.106329 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72810.670353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66162.029563 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66381.813465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72810.670353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66162.029563 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66381.813465 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -954,66 +870,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 73954 # number of writebacks -system.cpu.l2cache.writebacks::total 73954 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 74205 # number of writebacks +system.cpu.l2cache.writebacks::total 74205 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13293 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271967 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285260 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116708 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116708 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388623 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401915 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388623 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401915 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 845706258 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14164824509 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15010530767 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116864 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116864 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13293 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388831 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 402124 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13293 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388831 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 402124 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 801329759 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14314442009 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15115771768 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6731491626 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6731491626 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 845706258 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20896316135 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21742022393 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 845706258 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20896316135 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21742022393 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895642000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895642000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6549827374 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6549827374 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 801329759 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20864269383 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21665599142 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 801329759 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20864269383 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21665599142 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895641500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895641500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229787500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229787500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250214 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141490 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141506 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173232 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173232 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63625.207493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52092.839707 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52630.302787 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383733 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383733 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279476 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173297 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279476 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173297 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60282.085233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52633.010656 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52989.454421 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57678.065137 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57678.065137 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56046.578707 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56046.578707 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60282.085233 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53658.965934 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53877.906173 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60282.085233 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53658.965934 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53877.906173 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1021,13 +937,13 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1390568 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978915 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14049173 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391080 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.099472 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 107298250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978915 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1390774 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978892 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14051964 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391286 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.099982 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 107796250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978892 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1035,72 +951,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63152102 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63152102 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7814622 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814622 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5852326 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5852326 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182986 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182986 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199222 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199222 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13666948 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13666948 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13666948 # number of overall hits -system.cpu.dcache.overall_hits::total 13666948 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069470 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069470 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17259 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17259 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373840 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373840 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373840 # number of overall misses -system.cpu.dcache.overall_misses::total 1373840 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28875755759 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28875755759 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11035273137 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11035273137 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228925250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228925250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39911028896 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39911028896 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39911028896 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39911028896 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8884092 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8884092 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6156696 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6156696 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199222 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199222 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15040788 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15040788 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15040788 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15040788 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120380 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120380 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049437 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049437 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086189 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086189 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091341 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091341 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091341 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091341 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27000.061487 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27000.061487 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36256.113076 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36256.113076 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13264.108581 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13264.108581 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29050.711070 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29050.711070 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63164291 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63164291 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7816324 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7816324 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853358 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853358 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183027 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183027 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199238 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199238 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13669682 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13669682 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13669682 # number of overall hits +system.cpu.dcache.overall_hits::total 13669682 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069509 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069509 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304562 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304562 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17233 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17233 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374071 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374071 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374071 # number of overall misses +system.cpu.dcache.overall_misses::total 1374071 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29019471009 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29019471009 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10854033885 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10854033885 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228736500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228736500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39873504894 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39873504894 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39873504894 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39873504894 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8885833 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8885833 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157920 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157920 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200260 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200260 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199238 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199238 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15043753 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15043753 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15043753 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15043753 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120361 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120361 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086053 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086053 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27133.451901 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27133.451901 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35638.175101 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35638.175101 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.167760 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.167760 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29018.518617 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29018.518617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29018.518617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29018.518617 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1109,54 +1025,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835114 # number of writebacks -system.cpu.dcache.writebacks::total 835114 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069470 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069470 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304370 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304370 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17259 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17259 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373840 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373840 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373840 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373840 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26604805241 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26604805241 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10372104863 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10372104863 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194393750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194393750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36976910104 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36976910104 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36976910104 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36976910104 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011442000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011442000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.writebacks::writebacks 835359 # number of writebacks +system.cpu.dcache.writebacks::total 835359 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069509 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069509 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304562 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304562 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17233 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17233 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1374071 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374071 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374071 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374071 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26755042991 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26755042991 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10192844115 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10192844115 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194257500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194257500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36947887106 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36947887106 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36947887106 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36947887106 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011441500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011441500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120380 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120380 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049437 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049437 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086189 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086189 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091341 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091341 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24876.626031 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24876.626031 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34077.290347 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34077.290347 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11263.326380 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11263.326380 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120361 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120361 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086053 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086053 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25016.192469 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25016.192469 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33467.222158 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33467.222158 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.413393 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.413393 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1164,31 +1080,31 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 105179195 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2022861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022844 # Transaction distribution +system.cpu.toL2Bus.throughput 105199341 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2023010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022993 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 835114 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835359 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 345905 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304355 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858038 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3650630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5508668 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59456576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142531220 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 201987796 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 201977684 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2425850000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 346097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304546 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5509594 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59465280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142559956 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 202025236 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 202015188 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2426388000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1396163258 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1396297259 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2191612646 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2187438394 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- -- cgit v1.2.3