From a850fc916f06f05c1c55d634cdb2b230a7c23d11 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 15 Oct 2012 08:08:06 -0400 Subject: Stats: Update stats for use of two-level builder This patch updates the name of the l2 stats. --- .../alpha/linux/tsunami-simple-atomic/stats.txt | 160 +++++----- .../alpha/linux/tsunami-simple-timing/stats.txt | 340 ++++++++++----------- 2 files changed, 250 insertions(+), 250 deletions(-) (limited to 'tests/quick/fs/10.linux-boot/ref/alpha') diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 179af31f5..a50f49017 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -38,86 +38,86 @@ system.physmem.bw_total::cpu.inst 469015 # To system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 992301 # number of replacements -system.l2c.tagsinuse 65424.374305 # Cycle average of tags in use -system.l2c.total_refs 2433239 # Total number of references to valid blocks. -system.l2c.sampled_refs 1057464 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.301014 # Average number of references to valid blocks. -system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.998297 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 811229 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1718026 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 833491 # number of Writeback hits -system.l2c.Writeback_hits::total 833491 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187229 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 906797 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 998458 # number of demand (read+write) hits -system.l2c.demand_hits::total 1905255 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 906797 # number of overall hits -system.l2c.overall_hits::cpu.data 998458 # number of overall hits -system.l2c.overall_hits::total 1905255 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 927640 # number of ReadReq misses -system.l2c.ReadReq_misses::total 941046 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 117117 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 1044757 # number of demand (read+write) misses -system.l2c.demand_misses::total 1058163 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 13406 # number of overall misses -system.l2c.overall_misses::cpu.data 1044757 # number of overall misses -system.l2c.overall_misses::total 1058163 # number of overall misses -system.l2c.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2963418 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2963418 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.357075 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.357075 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 74291 # number of writebacks -system.l2c.writebacks::total 74291 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 992301 # number of replacements +system.cpu.l2cache.tagsinuse 65424.374305 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2433239 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1057464 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.301014 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks +system.cpu.l2cache.writebacks::total 74291 # number of writebacks +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41686 # number of replacements system.iocache.tagsinuse 1.225570 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index c82eab488..88df9e22a 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -38,176 +38,176 @@ system.physmem.bw_total::cpu.inst 442760 # To system.physmem.bw_total::cpu.data 12941865 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1380789 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 18620018 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 336257 # number of replacements -system.l2c.tagsinuse 65308.063316 # Cycle average of tags in use -system.l2c.total_refs 2448454 # Total number of references to valid blocks. -system.l2c.sampled_refs 401419 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.099497 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55656.590733 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4765.137084 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 4886.335499 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.849252 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.072710 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.074560 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996522 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 916463 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 814985 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1731448 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835257 # number of Writeback hits -system.l2c.Writeback_hits::total 835257 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 187565 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187565 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 916463 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1002550 # number of demand (read+write) hits -system.l2c.demand_hits::total 1919013 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 916463 # number of overall hits -system.l2c.overall_hits::cpu.data 1002550 # number of overall hits -system.l2c.overall_hits::total 1919013 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 271966 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285255 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 116861 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116861 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 13289 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 388827 # number of demand (read+write) misses -system.l2c.demand_misses::total 402116 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 13289 # number of overall misses -system.l2c.overall_misses::cpu.data 388827 # number of overall misses -system.l2c.overall_misses::total 402116 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.inst 691205000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 14147611000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14838816000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6077413000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6077413000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.inst 691205000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 20225024000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20916229000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 691205000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 20225024000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20916229000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 929752 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1086951 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2016703 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835257 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835257 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 304426 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304426 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 929752 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1391377 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2321129 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 929752 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1391377 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2321129 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.014293 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.250210 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.141446 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383873 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383873 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.014293 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.279455 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173242 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.014293 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.279455 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173242 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52013.319287 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.778208 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52019.477310 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 19076.923077 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40019.778208 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40019.466793 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.485149 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40005.485149 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements system.iocache.tagsinuse 1.347775 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -- cgit v1.2.3