From b1a58933e07d7af0eb5f43942f8ad9bc93f28039 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 27 Jul 2012 16:08:05 -0400 Subject: stats: update stats for icache change not allowing dirty data --- .../arm/linux/realview-simple-atomic/config.ini | 8 +- .../ref/arm/linux/realview-simple-atomic/simout | 8 +- .../ref/arm/linux/realview-simple-atomic/stats.txt | 456 ++++++++++----------- 3 files changed, 235 insertions(+), 237 deletions(-) (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic') diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index f14835c6b..59476048e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -191,7 +191,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -252,9 +252,9 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] @@ -665,7 +665,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 4dbfc774f..5f92f06af 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:35:36 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 00:54:29 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2332330037000 because m5_exit instruction encountered +Exiting @ tick 2332810264000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 176436ee7..e8bc29aac 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.332330 # Number of seconds simulated -sim_ticks 2332330037000 # Number of ticks simulated -final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.332810 # Number of seconds simulated +sim_ticks 2332810264000 # Number of ticks simulated +final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1988795 # Simulator instruction rate (inst/s) -host_op_rate 2567201 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78099767101 # Simulator tick rate (ticks/s) -host_mem_usage 382744 # Number of bytes of host memory used -host_seconds 29.86 # Real time elapsed on the host -sim_insts 59392246 # Number of instructions simulated -sim_ops 76665494 # Number of ops (including micro ops) simulated +host_inst_rate 1498673 # Simulator instruction rate (inst/s) +host_op_rate 1927201 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57874436068 # Simulator tick rate (ticks/s) +host_mem_usage 388524 # Number of bytes of host memory used +host_seconds 40.31 # Real time elapsed on the host +sim_insts 60408639 # Number of instructions simulated +sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9071568 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9071632 # Number of bytes read from this memory +system.physmem.bytes_read::total 121450608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory -system.physmem.bytes_written::total 6718856 # Number of bytes written to this memory +system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17218 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141777 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118171 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141778 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118174 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811814 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 302269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3889487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52072569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 302269 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 302269 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1587700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2880748 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1587700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 302262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3888714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52061931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302262 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 302269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5182536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54953317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,103 +61,103 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 62240 # number of replacements -system.l2c.tagsinuse 50004.786190 # Cycle average of tags in use -system.l2c.total_refs 1717775 # Total number of references to valid blocks. -system.l2c.sampled_refs 127625 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.459549 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2316513323500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36897.037256 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 2.960071 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.993930 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 7014.608709 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6089.186223 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563004 # Average percentage of cache occupancy +system.l2c.replacements 62243 # number of replacements +system.l2c.tagsinuse 50007.272909 # Cycle average of tags in use +system.l2c.total_refs 1669922 # Total number of references to valid blocks. +system.l2c.sampled_refs 127628 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.084292 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.107034 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.092914 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.763012 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 7534 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 838895 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 364444 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1214024 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 642748 # number of Writeback hits -system.l2c.Writeback_hits::total 642748 # number of Writeback hits +system.l2c.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.763050 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 366771 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1216278 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 592643 # number of Writeback hits +system.l2c.Writeback_hits::total 592643 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 113737 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113737 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 7534 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 838895 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 478181 # number of demand (read+write) hits -system.l2c.demand_hits::total 1327761 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 7534 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 3151 # number of overall hits -system.l2c.overall_hits::cpu.inst 838895 # number of overall hits -system.l2c.overall_hits::cpu.data 478181 # number of overall hits -system.l2c.overall_hits::total 1327761 # number of overall hits +system.l2c.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113739 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 838871 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 480510 # number of demand (read+write) hits +system.l2c.demand_hits::total 1330017 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 7507 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3129 # number of overall hits +system.l2c.overall_hits::cpu.inst 838871 # number of overall hits +system.l2c.overall_hits::cpu.data 480510 # number of overall hits +system.l2c.overall_hits::total 1330017 # number of overall hits system.l2c.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 10602 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 9870 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20480 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133469 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133469 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 9871 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20483 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2919 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133468 # number of ReadExReq misses system.l2c.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 10602 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 10604 # number of demand (read+write) misses system.l2c.demand_misses::cpu.data 143339 # number of demand (read+write) misses -system.l2c.demand_misses::total 153949 # number of demand (read+write) misses +system.l2c.demand_misses::total 153951 # number of demand (read+write) misses system.l2c.overall_misses::cpu.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu.inst 10602 # number of overall misses +system.l2c.overall_misses::cpu.inst 10604 # number of overall misses system.l2c.overall_misses::cpu.data 143339 # number of overall misses -system.l2c.overall_misses::total 153949 # number of overall misses -system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 849497 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 374314 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1234504 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 642748 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 642748 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 849497 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 621520 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1481710 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 849497 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 621520 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1481710 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.012480 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.026368 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.539910 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539910 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012480 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.230627 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.103900 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.012480 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.230627 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.103900 # miss rate for overall accesses +system.l2c.overall_misses::total 153951 # number of overall misses +system.l2c.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1483968 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1483968 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103743 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103743 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -166,8 +166,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57860 # number of writebacks -system.l2c.writebacks::total 57860 # number of writebacks +system.l2c.writebacks::writebacks 57863 # number of writebacks +system.l2c.writebacks::total 57863 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -177,26 +177,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14971229 # DTB read hits -system.cpu.dtb.read_misses 7293 # DTB read misses -system.cpu.dtb.write_hits 11217018 # DTB write hits +system.cpu.dtb.read_hits 14971214 # DTB read hits +system.cpu.dtb.read_misses 7294 # DTB read misses +system.cpu.dtb.write_hits 11217004 # DTB write hits system.cpu.dtb.write_misses 2181 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3492 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 14978522 # DTB read accesses -system.cpu.dtb.write_accesses 11219199 # DTB write accesses +system.cpu.dtb.read_accesses 14978508 # DTB read accesses +system.cpu.dtb.write_accesses 11219185 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26188247 # DTB hits -system.cpu.dtb.misses 9474 # DTB misses -system.cpu.dtb.accesses 26197721 # DTB accesses -system.cpu.itb.inst_hits 60403303 # ITB inst hits +system.cpu.dtb.hits 26188218 # DTB hits +system.cpu.dtb.misses 9475 # DTB misses +system.cpu.dtb.accesses 26197693 # DTB accesses +system.cpu.itb.inst_hits 61431840 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -213,67 +213,67 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 60407774 # ITB inst accesses -system.cpu.itb.hits 60403303 # DTB hits +system.cpu.itb.inst_accesses 61436311 # ITB inst accesses +system.cpu.itb.hits 61431840 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 60407774 # DTB accesses -system.cpu.numCycles 4664583062 # number of cpu cycles simulated +system.cpu.itb.accesses 61436311 # DTB accesses +system.cpu.numCycles 4665543516 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 59392246 # Number of instructions committed -system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses +system.cpu.committedInsts 60408639 # Number of instructions committed +system.cpu.committedOps 77681819 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68795605 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2136013 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls -system.cpu.num_int_insts 68281415 # number of integer instructions +system.cpu.num_func_calls 2136008 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7904929 # number of instructions that are conditional controls +system.cpu.num_int_insts 68795605 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 345981857 # number of times the integer registers were read -system.cpu.num_int_register_writes 73062916 # number of times the integer registers were written +system.cpu.num_int_register_reads 349324274 # number of times the integer registers were read +system.cpu.num_int_register_writes 74103608 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27361692 # number of memory refs -system.cpu.num_load_insts 15639569 # Number of load instructions -system.cpu.num_store_insts 11722123 # Number of store instructions -system.cpu.num_idle_cycles 4586814358.980880 # Number of idle cycles -system.cpu.num_busy_cycles 77768703.019120 # Number of busy cycles -system.cpu.not_idle_fraction 0.016672 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983328 # Percentage of idle cycles +system.cpu.num_mem_refs 27361637 # number of memory refs +system.cpu.num_load_insts 15639527 # Number of load instructions +system.cpu.num_store_insts 11722110 # Number of store instructions +system.cpu.num_idle_cycles 4586746360.692756 # Number of idle cycles +system.cpu.num_busy_cycles 78797155.307244 # Number of busy cycles +system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983111 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu.icache.replacements 850612 # number of replacements -system.cpu.icache.tagsinuse 511.678549 # Cycle average of tags in use -system.cpu.icache.total_refs 59554939 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 851124 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 69.972106 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 5708999000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.678549 # Average occupied blocks per requestor +system.cpu.icache.replacements 850590 # number of replacements +system.cpu.icache.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu.icache.total_refs 60583498 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 851102 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 71.182418 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59554939 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59554939 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59554939 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59554939 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59554939 # number of overall hits -system.cpu.icache.overall_hits::total 59554939 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 851124 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 851124 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 851124 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 851124 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 851124 # number of overall misses -system.cpu.icache.overall_misses::total 851124 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60406063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60406063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60406063 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60406063 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014090 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014090 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014090 # miss rate for overall accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits +system.cpu.icache.overall_hits::total 60583498 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses +system.cpu.icache.overall_misses::total 851102 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -282,58 +282,56 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 50093 # number of writebacks -system.cpu.icache.writebacks::total 50093 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 623347 # number of replacements -system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use -system.cpu.dcache.total_refs 23628362 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 623859 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.874523 # Average number of references to valid blocks. +system.cpu.dcache.replacements 623337 # number of replacements +system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13180074 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13180074 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9962087 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9962087 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236035 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236035 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247222 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247222 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23142161 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23142161 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23142161 # number of overall hits -system.cpu.dcache.overall_hits::total 23142161 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 365465 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 365465 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250150 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250150 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11188 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11188 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 615615 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 615615 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 615615 # number of overall misses -system.cpu.dcache.overall_misses::total 615615 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13545539 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13545539 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10212237 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10212237 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247223 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits +system.cpu.dcache.overall_hits::total 23142138 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses +system.cpu.dcache.overall_misses::total 615611 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses @@ -346,8 +344,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 592655 # number of writebacks -system.cpu.dcache.writebacks::total 592655 # number of writebacks +system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks +system.cpu.dcache.writebacks::total 592643 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use -- cgit v1.2.3